vhdl问题

library ieee;
use ieee.std_logic_1164.all;
entity vhdl1 is
port (a,b,c:in std_logic;
                  re:in std_logic;

                  yut std_logic_vector(1 downto 0));
end entity vhdl1;


architecture responder_table of vhdl1 is
shared variable door:bit:='0';
begin


process(a,b,c)is
variable con:std_logic_vector(2 downto 0);
begin
        con:=a&b&c;
if(door='0') then
        case con is
                when "100"=>y<="01";
                when "010"=>y<="10";
                when "001"=>y<="11";
                when others => y<="XX";
        end case;
        door:='1';
end if;
end process;


process(re) is
begin
        door:='0';
end process;

end architecture responder_table;


不能运行，谢谢大家！