下面是我的程序:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity colormap is
port( hloc:in std_logic_vector(10 downto 0);
vloc:in std_logic_vector(10 downto 0);
rgbxut std_logic_vector(7 downto 0);
hlocat: inout std_logic_vector(10 downto 0));
end colormap;
architecture Behavioral of colormap is
signal hlocat1:integer:=220;
signal i:integer:=0;
begin
process(hloc,vloc)
begin
rgbx<="00000000";
if (hloc>=100 and hloc<=550 and vloc>=60 and vloc<=360) then
if (hloc>=320 and hloc<=330) then
rgbx<="00011100";
else
rgbx<="11100000";
end if;
end if;
i<=i+1;
if i>=60000 then
i<=0;
hlocat1<=hlocat1+1;
if hlocat1 >500 then
hlocat1<=420;
end if;
end if;
if (hloc>=hlocat1 and hloc<=hlocat1+5 and vloc>=205 and vloc<=210) then
i<=i+1;
if i>=60000 then
i<=0;
hlocat1<=hlocat1+1;
if hlocat1 >500 then
hlocat1<=420;
end if;
end if;
rgbx<="00000011";
end if;