三分频、五分频程序

三分频程序如下：
library IEEE;
use IEEE.STD_LOGIC_116 4.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity division5 is
port (clk: in std_logic;
     out1: out std_logic);
     end division5;
architecture Behavioral of division5 is
      signal division2,division4  :std_logic;
      signal temp1,temp2:integer range 0 to 10;
begin
p1:process(clk)
begin
if rising_edge(clk) then
temp1<=temp1+1;
if temp1=1 then
division2<='1';
elsif temp1=2 then
division2<='0';
temp1<=0;
end if;
end if;
end process p1;

p2:process(clk)
begin
if clk'event and clk='0' then
temp2<=temp2+1;
if temp2=1 then
division4<='1';
elsif temp2=2 then
division4<='0';
temp2<=0;
end if;
end if;
end process p2;
p3:process(division2,division4)
begin
out1<=division2 or division4;
end process p3;
end Behavioral;

五分频程序如下：
library IEEE;
use IEEE.STD_LOGIC_116 4.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity division5 is
port (clk: in std_logic;
     out1: out std_logic);
     end division5;
architecture Behavioral of division5 is
      signal division2,division4  :std_logic;
      signal temp1,temp2:integer range 0 to 10;
begin
p1:process(clk)
begin
if rising_edge(clk) then
temp1<=temp1+1;
if temp1=2 then
division2<='1';
elsif temp1=4 then
division2<='0';
temp1<=0;
end if;
end if;
end process p1;
p2:process(clk)
begin
if clk'event and clk='0' then
temp2<=temp2+1;
if temp2=2 then
division4<='1';
elsif temp2=4 then
division4<='0';
temp2<=0;
end if;
end if;
end process p2;
p3:process(division2,division4)
begin
out1<=division2 or division4;
end process p3;
end Behavioral;

希望对大家有用！

三分频、五分频程序

好贴！

三分频的波形图，有疑问的我可以帮忙解释。

这是什么代码啊？我怎么看不懂啊？但又有点眼熟。

vhdl代码！

vhdl代码！
蓝余 发表于 2011-7-4 18:46

    xiexie

不错，收藏了

有任意分频的

改改参数就能实现其他分频了。