VHDL 不知道错在哪了 我是一个初学者

library ieee;
use ieee.std_logic_1164.all;

entity par_ser is
port(
      clock  :   in  std_logic;
      parallel_in  : in  std_logic_vector(7 downto 0);
      serial_out   : out  std_logic
     );
     
end par_ser;

architecture behavior of par_ser is
signal parallel: std_logic_vector(7 downto 0);
begin
  parallel(7 downto 0)<=parallel_in(7 downto 0);
  process(clock)
  begin
   if clock'event and clock='1' then
       serial_out<=parallel(0);
      for I in 0 to 6 loop
         parallel(I)<=parallel(I+1);
      end loop;
   end if;   
  end process;
end behavior;

编译的时候说是
Error (10031): Net "parallel[6]" at par_ser.vhd(22) is already driven by input port "parallel_in[6]", and cannot be driven by another signal
Error (10032): "parallel_in[6]" was declared at par_ser.vhd(7)
Error (10031): Net "parallel[5]" at par_ser.vhd(22) is already driven by input port "parallel_in[5]", and cannot be driven by another signal
Error (10032): "parallel_in[5]" was declared at par_ser.vhd(7)
Error (10031): Net "parallel[4]" at par_ser.vhd(22) is already driven by input port "parallel_in[4]", and cannot be driven by another signal
Error (10032): "parallel_in[4]" was declared at par_ser.vhd(7)
Error (10031): Net "parallel[3]" at par_ser.vhd(22) is already driven by input port "parallel_in[3]", and cannot be driven by another signal
Error (10032): "parallel_in[3]" was declared at par_ser.vhd(7)
Error (10031): Net "parallel[2]" at par_ser.vhd(22) is already driven by input port "parallel_in[2]", and cannot be driven by another signal
Error (10032): "parallel_in[2]" was declared at par_ser.vhd(7)
Error (10031): Net "parallel[1]" at par_ser.vhd(22) is already driven by input port "parallel_in[1]", and cannot be driven by another signal
Error (10032): "parallel_in[1]" was declared at par_ser.vhd(7)
Error (10031): Net "parallel[0]" at par_ser.vhd(22) is already driven by input port "parallel_in[0]", and cannot be driven by another signal
Error (10032): "parallel_in[0]" was declared at par_ser.vhd(7)

解决方法（官方）：

Check the Verilog HDL module or VHDL entity to locate conflicting assignments to the same signal. Remove all but one of the assignments
我的理解是：你的parallel在16行已经赋值了，22行又赋值，这两个是同时进行的，所以出错了

解决方法（官方）：

Check the Verilog HDL module or VHDL entity to locate conflicting assignments to the same signal. Remove all but one of the assignments
我的理解是：你的parallel在16行已经赋值了，22行又赋值，这两个是同时进行的，所以出错了

你试着把 ‘parallel(7 downto 0)<=parallel_in(7 downto 0);’这句放到process begin后面，看看行不行

似乎也不行

错误提示是什么

Error (10818): Can't infer register for "parallel[0]" at par_ser.vhd(21) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "parallel[1]" at par_ser.vhd(21) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "parallel[2]" at par_ser.vhd(21) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "parallel[3]" at par_ser.vhd(21) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "parallel[4]" at par_ser.vhd(21) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "parallel[5]" at par_ser.vhd(21) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "parallel[6]" at par_ser.vhd(21) because it does not hold its value outside the clock edge
Error (10822): HDL error at par_ser.vhd(21): couldn't implement registers for assignments on this clock edge

好了 把parallel(7 downto 0)<=parallel_in(7 downto 0);放到process里面 在给他加个使能信号就OK了
很谢谢你啊

加使能信号，呵呵，又学了一课