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library ieee; 
use ieee.std_logic_1164.all        ; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 
  
entity twice is 
 port (clk,rst:in std_logic; 
       clk_temp:inout std_logic; 
       d_out:inout std_logic; 
       d_outn:inout std_logic; 
       clk_out ut std_logic); 
end twice; 
  
architecture rtl of twice is  
begin 
process(clk_temp,rst) 
begin 
        if(rst='1') then 
                d_out<='0'; 
        else  
                if(clk_temp'event and clk_temp='1') then 
                        d_out<=d_outn; 
                 end if; 
         end if; 
end process; 
  
clk_temp<=clk xor d_out; 
  
clk_out<=clk_temp; 
  
d_outn<=not d_out; 
end rtl; |   
 
 
 
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