/*
*/
module mi2c_top (
clock ,
reset,
a,
di,
wr,
sel,
scl,
sda,
da,
noe,
intr
);
input clock ,reset ;
input [2:0] a ;
input [7:0] di ;
input wr ,sel ;
output [7:0] da ;
output noe ,intr ;
inout tri1 scl ;
inout tri1 sda ;
wire isda,iscl,osda,oscl ;
mi2c U_mi2c(
.CLK (clock),
.NRST (reset),
.A (a),
.DI (di),
.WR (wr),
.SEL (sel),
.ISCL (iscl),
.ISDA (isda),
.DA (da),
.NOE (noe),
.INTR (intr),
.OSCL (oscl),
.OSDA (osda)
);
assign iscl = scl ;
assign isda = sda ;
assign scl = (oscl == 1'd0) ? 1'd0 : 1'dz ;
assign sda = (osda == 1'd0) ? 1'd0 : 1'dz ;
endmodule
这个是我用在FPGA中自己设计的顶层,合并input scl,sda 和output scl,sda的。图片中是notpad打开这个.v的截图 |