VHDL问题，想不明白只好求教了

想了很久实在不知道怎么办了
求大家帮帮忙
我想写的这个元件功能是这样的，one_yuan，two_yuan，five_yuan是可重复投币按钮，按一下表示投一次对应钱数，然后在have_pay输出一共投了多少钱，reset高电平时清零
以下是我写的
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library ieee;
use ieee.std_logic_1164.all;
entity test is
port(one_yuan,two_yuan,five_yuan,reset：in std_logic;
     have_pay：out integer range 0 to 99);
end entity test;
architecture bhv of test is
begin
process(reset,one_yuan,two_yuan,five_yuan)
variable pay_tmp:integer range 0 to 99;
begin
if reset='1' then pay_tmp:=0;
elsif one_yuan'event and one_yuan='1' then pay_tmp:=pay_tmp+1;
elsif two_yuan'event and two_yuan='1' then pay_tmp:=pay_tmp+2;
elsif five_yuan'event and five_yuan='1' then pay_tmp:=pay_tmp+5;
end if;
have_pay<=pay_tmp;    --如果这句去掉编译就能通过，当然，去掉了have_pay就没有值
end process;
end architecture bhv;
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按以上编译的错误信息是（错误提示很多，但好像是同一个错误导致）

Error (10820): Netlist error at test.vhd(12): can't infer register for pay_tmp[0] because its behavior depends on the edges of multiple distinct clocks
Error (10818): Can't infer register for "pay_tmp[0]" at test.vhd(12) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "pay_tmp[0]" at test.vhd(12)
Error (10820): Netlist error at test.vhd(12): can't infer register for pay_tmp[1] because its behavior depends on the edges of multiple distinct clocks
Error (10818): Can't infer register for "pay_tmp[1]" at test.vhd(12) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "pay_tmp[1]" at test.vhd(12)
Error (10820): Netlist error at test.vhd(12): can't infer register for pay_tmp[2] because its behavior depends on the edges of multiple distinct clocks
Error (10818): Can't infer register for "pay_tmp[2]" at test.vhd(12) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "pay_tmp[2]" at test.vhd(12)
Error (10820): Netlist error at test.vhd(12): can't infer register for pay_tmp[3] because its behavior depends on the edges of multiple distinct clocks
Error (10818): Can't infer register for "pay_tmp[3]" at test.vhd(12) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "pay_tmp[3]" at test.vhd(12)
Error (10820): Netlist error at test.vhd(12): can't infer register for pay_tmp[4] because its behavior depends on the edges of multiple distinct clocks
Error (10818): Can't infer register for "pay_tmp[4]" at test.vhd(12) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "pay_tmp[4]" at test.vhd(12)
Error (10820): Netlist error at test.vhd(12): can't infer register for pay_tmp[5] because its behavior depends on the edges of multiple distinct clocks
Error (10818): Can't infer register for "pay_tmp[5]" at test.vhd(12) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "pay_tmp[5]" at test.vhd(12)
Error (10820): Netlist error at test.vhd(12): can't infer register for pay_tmp[6] because its behavior depends on the edges of multiple distinct clocks
Error (10818): Can't infer register for "pay_tmp[6]" at test.vhd(12) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "pay_tmp[6]" at test.vhd(12)
Error (10822): HDL error at test.vhd(13): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at test.vhd(14): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at test.vhd(15): couldn't implement registers for assignments on this clock edge
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 18 errors, 0 warnings
        Info: Allocated 155 megabytes of memory during processing
        Error: Processing ended: Wed Dec 03 12:27:24 2008
        Error: Elapsed time: 00:00:03
Error: Quartus II Full Compilation was unsuccessful. 18 errors, 0 warnings

如果***为非全局时钟引脚，也就是普通IO,建议不要用if ***'event and *** = '1' then 来检测上升下降沿！可以引入全局时钟信号，通过对全局时钟信号的检测，来达到获取IO引脚跳变的目的。

have_pay<=pay_tmp;  把这句放process外面 并且定义pay_tmp 为 signal

非常到位，顶蓝余版主！！！！！