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以下是滤波模块的VHDL描述
library IEEE;
use IEEE.Std_logIC_1164.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity fitter is port(clk,A:in std_logic; AOUT ut std_logic); end entity filter;
architecture Crane of filter is
signal data0,data1,data2,data3,data4,data5:integer range 0 to 1;
signal dataall:integer range 0 to 7;
begin
process(clk)
begin
if clk'event and clk='1' then
if A='1' then data0<=1;else data0<=0;end if;
data1<=data0;data2<=data1;data3<=data2;data4<=data3;data5<=data4;
dataall<=data0+data1+data2+data3+data4+data5;
if (dataall>=3) then AOUT<='1'; else AOUT<='0'; end if;
end if;
end process;
end architecture Crane; |
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