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32位超前进位加法器CLA的FPGA实现
其调用的子模块无需修改,沿用即可。
module cla32_adder (a, b, cin, s, cout); //顶层模块
input [31:0] a, b;
input cin;
output [31:0] s;
output cout;
wire[7:0] gg, gp, gc; //
wire[3:0] ggg, ggp, ggc; //
wire gggg, gggp; //
//first level
bitslice4 b0(a[ 3: 0], b[ 3: 0], gc[0], s[ 3: 0], gp[0], gg[0]);
bitslice4 b1(a[ 7: 4], b[ 7: 4], gc[1], s[ 7: 4], gp[1], gg[1]);
bitslice4 b2(a[11: 8], b[11: 8], gc[2], s[11: 8], gp[2], gg[2]);
bitslice4 b3(a[15:12], b[15:12], gc[3], s[15:12], gp[3], gg[3]);
bitslice4 b4(a[19:16], b[19:16], gc[4], s[19:16], gp[4], gg[4]);
bitslice4 b5(a[23:20], b[23:20], gc[5], s[23:20], gp[5], gg[5]);
bitslice4 b6(a[27:24], b[27:24], gc[6], s[27:24], gp[6], gg[6]);
bitslice4 b7(a[31:28], b[31:28], gc[7], s[31:28], gp[7], gg[7]);
//second level
cla4 c0 (gp[3:0], gg[3:0], ggc[0], gc[3:0], ggp[0], ggg[0]);
cla4 c1 (gp[7:4], gg[7:4], ggc[1], gc[7:4], ggp[1], ggg[1]);
assign ggp[3:2] = 2'b11;
assign ggg[3:2] = 2'b00;
//third level
cla4 c2 (ggp[3:0], ggg[3:0], cin, ggc[3:0], gggp, gggg);
assign cout = gggg | (gggp & cin);
endmodule
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