某知名通信五大设备公司招聘RRH Senior FPGA/HW Engineer

发布日期：        2010-02-21        工作地点：        上海        招聘人数：        1
工作年限：        八年以上        语言要求：        英语 良好        学    历：        本科
职位描述
某知名通信五大设备公司招聘RRH Senior FPGA/HW Engineer - DIF/DPD/CFR
工作地点：上海
薪资范围：20-40W年薪
投递简历邮箱：a300027@vastsea.com
Title: RRH Senior FPGA/HW Engineer - DIF/DPD/CFR

Job Description
Remote Radio Head (The “RRH” hereafter) is a part of base station used at wireless mobile access network. RRH’s main functions are RF/base-band signal filtering, amplification, frequency converting, ADC and DAC, antennal supervision. It interfaces with BBU with standard based optical links to make a complete base station (Node-B or eNode-B). We are looking for high talents to join this challenging R&D team in Alcatel Lucent China, to define, develop and delivery competitive RRH products for 3G and 4G wireless network.
As a senior member of the R&D team, the candidate will be a key contributor for RRH design and development, with the focus on Algorithm, implementation and testing of functions as: Digital Intermediate Frequency (DIF), Digital Pre-Distortion (DPD) and Crest Factor Reduction. In detail, the capable candidates will have the opportunity to join the effort in RRH architecture design, leading the development, performance tuning and qualification of DIF/DPD/CFR functions.

Responsibilities
1. Education background: bachelor with 8+ years experience, MS/PHD with 5+ years experience, in algorithm definition and FPGA implementation
2. Major in: telecommunication, computer science, or related
3. Solid knowledge in signal processing algorithms and FPGA implementation in one or more of the following area: (1) DIF and pulse shaping, (2) DPD, (3) CFR;
4. Be familiar RF design, and be able to support RRH architecture definition by providing the evaluation and proposal scheme in DIF/DPD/CRF;
5. Be able to define the FPGA architecture with functional requirements and Algorithms as the inputs; Be able to define competitive solutions with the trade-off on the performance and cost;
6. Strong experience in using variance FPGA tools, very good at coding with VHDL or Verilog, good at the FPGA tool chain to do the synthesize, placement and routing. Good at design optimization;
7. Good at communication: English, good, both written and oral
8. Other requirements: Capability to adapt rapidly in a challenging job environment; Be good at work independently and also good at team working;
9. Direct experience in RRH design / development is high preferred;

联系方式
电子邮箱：        a300027@vastsea.com;zhaopin001@vastsea.com

某知名通信五大设备公司招聘RRH Senior FPGA/HW Engineer