MaxPlusII中的VHDL问题！

这个程序为什么在MaxPlusII中编译不了？
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE packexp IS
  FUNCTION max (a,b : IN STD_LOGIC_VECTOR)    RETURN STD_LOGIC_VECTOR;
END;

PACKAGE BODY packexp IS
  FUNCTION max (a,b : IN STD_LOGIC_VECTOR)    RETURN STD_LOGIC_VECTOR IS
  Variable TEMP : std_logic_vector;
  BEGIN
    IF (a > b) THEN return a;
    ELSE            return b;    END IF;
  END FUNCTION max;
END;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.packexp.ALL;
ENTITY AXAMP IS
  PORT ( dat1,dat2 : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
         dat3,dat4 : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
         out1,out2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END;

ARCHITECTURE BHV OF AXAMP IS
BEGIN
  out1 <= max (dat1,dat2);
  PROCESS (dat3,dat4)
  BEGIN
    out2 <= max (dat3,dat4);
  END PROCESS;
END;

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