一简单vhdl程序问题，求高手指教
本帖最后由 fpgaw 于 2010-10-29 09:38 编辑这是我写的程序，想让它实现单稳态触发功能，但是变异不了，好像陷入了死循环 望高手指教！ 谢谢
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tou is
port(
-- Input ports
clk: inSTD_LOGIC;
intou: inSTD_LOGIC;
-- Output ports
otou: out STD_LOGIC
);
end entity;
architecture tou_1 of tou is
begin
p1:Process (intou)
variable counter : integer range 0 to 200;
begin
otou<='1';
while (counter<100) loop
if(clk'event and clk='1') then
counter :=counter+1;
end if;
end loop;
counter :=0;
otou<='0';
end process p1;
end tou_1; 6
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