没有输出block ram ！！
大家好我用 Block Memory Generator 4.3产生一个 single port block ram.
I set:
Write Width:32
Read Width:32
Write Depth:128
Read Depth:128
Write First
Always Enable
Register Port A Output of Memory Core
Pipeline Stages within Mux :0
仿真结果是douta一直为0，请教高手问题出在了哪里，谢谢！
The module is:
module test5(clka, wea, addra, dina, douta
);
input clka;
input wea;
input addra;
input dina;
output douta;
Block_RAM BRAM (
.clka(clk),
.wea(wea), // Bus
.addra(addra), // Bus
.dina(dina), // Bus
.douta(douta)); // Bus
endmodule
module test5_tb;
// Inputs
reg clka;
reg wea;
reg addra;
reg dina;
// Outputs
wire douta;
// Instantiate the Unit Under Test (UUT)
test5 uut (
.clka(clka),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta)
);
initial begin
// Initialize Inputs
clka = 0;
wea = 0;
addra = 0;
dina = 0;
// Wait 100 ns for global reset to finish
#100;
addra = 23;
#20;
addra = 12;
#10;
wea = 1;
dina = 256;
#20;
addra = 23;
dina = 856;
#30;
wea = 0;
#100;
addra = 23;
#20;
addra = 12;
// Add stimulus here
end
always #5 clka = ~clka;
endmodule 测试模块中怎么没有$finish。你加上这个试试看。
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