quartus 编写的RAM读写出现错误
Error (10200): Verilog HDL Conditional Statement error at MC_v4.v(125): cannot match all operands in the condition expression to corresponding edges in the enclosing Always Construct's Event ControlError (10200): Verilog HDL Conditional Statement error at MC_v4.v(127): cannot match all operands in the condition expression to corresponding edges in the enclosing Always Construct's Event Control
Error: Can't elaborate top-level user hierarchy
我的程序是利用quartus自动生成的单口ram，还有锁相环pll,总线仲裁是9054的，那本分没错。主要是ram读写的问题。自己给了一个ram 输入数据。
程序如下
module quartus_ram(//时钟和复位
clk_in, rst_n,
//总线握手
hold, holda, blast_n, ads_n ,
ready_n,bterm_n,ccs_n ,
//地址数据读写信号
write_read, address_bus, data_bus
);
//clock
input rst_n ;
input clk_in ;
wire clk_glable;//全局时钟
wire clk_glable_test;
clk_pll clk_gen_0( .inclk0(clk_in),
.c0(clk_glable),
.c1(clk_glable_test));
//bus_arbitrate
supply1 vcc;
output bterm_n;
output ccs_n;
assign bterm_n = vcc ;
assign ccs_n = vcc ;
input hold ;
input blast_n ;
input ads_n;
output holda ;
output ready_n;
bus_arbitratearbitrate( .hold(hold),
.blast_n (blast_n),
.ads_n (ads_n),
.gclk (clk_glable),
.rst_n (rst_n),
.holda(holda) ,
.ready_n(ready_n)
);
//数据总线1 write 0 read
input write_read ;
inout data_bus ;
wiredata_local_in ;
reg data_local_out ;
assign data_local_in = data_bus ;
assign data_bus =(~write_read) ? data_local_out : 32'bzzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz ;
input address_bus;
reg enable ;
always @ (posedge clk_glable or negedge rst_n) begin
if (rst_n == 0 ) begin //复位
//channel_0_counter <= 0;
// channel_1_counter <= 0;
//dir <= 32'b1111_1111_1111_1111_1111_1111_1111_1111;
enable <= 32'b0000_0000_0000_0000_0000_0000_0000_0000;
data_local_out <= 32'b0000_0000_0000_0000_0000_0000_0000_0000;
//channel_0_send_p <= 800_000;
//to_zero_bit_buf <= 32'b0000_0000_0000_0000_0000_0000_0000_0000;
end
else if(ready_n == 1'b0 ) begin //数据和地址都已经准备好 1 write 0 read
if ( write_read == 1'b1 )
case (address_bus)
14'b00000000010001 : enable <= data_local_in ;
default : ;
endcase
else if( write_read == 1'b0) //读
case (address_bus)
//分频数据反馈
14'b00000000010010 : data_local_out <= dataout;
14'b00000000000101 : data_local_out <= 5;
default : data_local_out <= 32'b0000_0000_0000_0000_0000_0000_0000_0011;
endcase
end
end
//通道定时发生
wire addr;
regaddr_buf;
regdatain_buf;
regdatain;
reg wr;
wiredataout_buf;
regwr_addr_buf;
regrd_addr_buf;
regdataout;
assign addr=addr_buf;
ram ram_one(
.address(addr),
.clock(clk_glable),
.data(datain),
.wren(wr),
.q(dataout_buf));
always@(posedge clk_glable or negedge rst_n)
if(rst_n==0)
begin
datain_buf<=32'b0000_0000_0000_0000_0000_0000_0000_0000;
wr<=1;
end
else
begin
if(datain_buf>=32'b0000_0000_0000_0000_0000_0000_1100_1000)
wr<=0;
else
begin
datain_buf<=datain_buf+32'b0000_0000_0000_0000_0000_0000_0000_0001;
wr<=1;
end
end
always@(posedge clk_glable or negedge rst_n)
begin
if(wr==1) addr_buf<=wr_addr_buf;
else if(wr==0) addr_buf<=rd_addr_buf;
else
addr_buf<=8'b0000_0000;
end
always@(posedge clk_glable or negedge rst_n)
begin
if(rst_n==0)
begin
wr_addr_buf<=8'b0000_0000;
rd_addr_buf<=8'b0000_0000;
dataout<=32'b0000_0000_0000_0000_0000_0000_0000_0000;
datain<=32'b0000_0000_0000_0000_0000_0000_0000_0000;
end
else if(wr==1)
begin
wr_addr_buf<=wr_addr_buf+8'b0000_0001;
datain<=datain_buf;
end
else if(wr==0)
begin
rd_addr_buf<=rd_addr_buf+8'b0000_0001;
dataout<=dataout_buf;
end
end
endmodule 大家帮帮忙，我刚开始学 你可以调用个ip核。
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