我是初学者，我在网上下载了一个FPGA工程，有一处错误请哪位高手指点一下
/* CSL configuration is no longer supported. *//* Your CSL configuration has been saved here as part*/
/* of the process of converting cdb to tcf. */
/* INPUT mpeg2_encoder.cdb */
r=Lime]
/*Include Header File */
#include "mpeg2_encodercfg_csl.h"
#error "Please read the comment below to finish updating your project"
/*
* The following steps are required to use this file:
*
* 1.Modify any source files that use these structures to
* `#include <mpeg2_encodercfg_csl.h>`.These structure definitions were
* previously contained in <mpeg2_encodercfg.h>.
* 2.Call `CSL_init()` and `cslCfgInit()` from your application's main()
* function.This is necessary to initialize CSL and the assorted
* CSL handles.These functions were previously called by BIOS internally.
* 3.Remove the #error line above.
* 4.Update your linker options to include the CSL library for the device
* that you are using. This library name was listed in the original
* generated mpeg2_encodercfg.cmd file (e.g., "-lcsl6416.lib").
* 5.If you are using the 54x or 55x, you will need to create an additional
* linker .cmd file that includes the generated mpeg2_encodercfg.cmd file
* and adds section placement for the '.csldata' section.
*
* See the DSP/BIOS Setup Guide for more information.
*/
#pragma CODE_SECTION(cslCfgInit,".text:cslCfgInit")
/*Config Structures */
/* EMIFA_Config emifaCfg0
* comment <add comments here>
* External HOLD disable (NOHOLD) Enable Hold
* CLKOUT4 Enable (CLK4EN) Enabled to clock
* CLKOUT6 Enable (CLK6EN) Enabled to clock
* ECLKOUT1 Enable (EK1EN) Enabled to clock
* ECLKOUT2 Enable (EK2EN) Enabled to clock
* ECLKOUT1 High-Z Control (EK1HZ) High-Z during hold
* ECLKOUT2 High-Z Control (EK2HZ) Clock during hold
* ECLKOUT2 Rate (EK2RATE) 1/2x EMIF input clock
* Bus Request Mode access/refresh pending or in progress
* Memory Type (MTYPE) 64-bit SDRAM
* Read Strobe Width 0x3F
* Read Setup Width 0xF
* Read Hold Width 0x3
* Write Strobe Width 0x3F
* Write Setup Width 0xF
* Write Hold Width (WRHLD-WRHLDMSB) 0x3
* Turn around time (TA) 0x3
* Memory Type (MTYPE) 16-bit async. interf.
* Read Strobe Width 0xE
* Read Setup Width 0x2
* Read Hold Width 0x1
* Write Strobe Width 0xE
* Write Setup Width 0x7
* Write Hold Width (WRHLD - WHLDMSB) 0x2
* Turn around time (TA) 0x2
* Memory Type (MTYPE) 16-bit async. interf.
* Read Strobe Width 0xE
* Read Setup Width 0x2
* Read Hold Width 0x1
* Write Strobe Width 0xE
* Write Setup Width 0x7
* Write Hold Width 0x2
* Turn around time (TA) 0x2
* Memory Type (MTYPE) 8-bit async. interf.
* Read Strobe Width 0xE
* Read Setup Width 0x2
* Read Hold Width 0x1
* Write Strobe Width 0xE
* Write Setup Width 0x7
* Write Hold Width 0x2
* Turn around time (TA) 0x2
* Sync. interf. data read latency (SYNCRL) 2 cycles
* Sync. interf. data write latency (SYNCWL) 0 cycle
* CE Extension Register (CEEXT) Inactive
* Read Enable Enable (RENEN) ADS Mode
* Synchronization Clock (SNCCLK) Sync. to ECLKOUT1
* Sync. interf. data read latency (SYNCRL) 2 cycles
* Sync. interf. data write latency (SYNCWL) 0 cycle
* CE Extension Register (CEEXT) Inactive
* Read Enable Enable (RENEN) ADS Mode
* Synchronization Clock (SNCCLK) Sync. to ECLKOUT1
* Sync. interf. data read latency (SYNCRL) 2 cycles
* Sync. interf. data write latency (SYNCWL) 0 cycle
* CE Extension Register (CEEXT) Inactive
* Read Enable Enable (RENEN) ADS Mode
* Synchronization Clock (SNCCLK) Sync. to ECLKOUT1
* Sync. interf. data read latency (SYNCRL) 2 cycles
* Sync. interf. data write latency (SYNCWL) 0 cycle
* CE Extension Register (CEEXT) Inactive
* Read Enable Enable (RENEN) ADS Mode
* Synchronization Clock (SNCCLK) Sync. to ECLKOUT1
* TRC = trc/(eclkout1 period-1) (TRC) 0x5
* TRP = trp/(eclkout1 period-1) (TRP) 0x1
* TRCD = trcd/(eclkout1 period-1) (TRCD) 0x1
* Initialization of all SDRAMs (INIT) Initialize
* SDRAM Refresh Enable (RFEN) Enable
* Column Size (SDCSZ) 8 addresses
* Row Size (SDRSZ) 12 addresses
* Bank Size (SDBSZ) Four banks
* Self-refresh mode(SLFRFR) Disable
* Refresh Period (ECLKOU1 cycles) 0x81B
* Extra Refreshes Ctrl. (XRFR) 0x1
* CAS Latency (TCL) 0x3
* tras = TRAS + 1 (ECLKOU1 cyc.) 0x7
* trrd = TRRD (2 or 3 ECLKOU1 cyc.) 0x2
* twr= TWR + 1 (ECLKOU1 cyc.) 0x3
* thzp = THZP + 1 (ECLKOU1 cyc.) 0x3
* READ-To-READ (ECLKOU1 cyc.) 0x2
* READ-To-DEAC/DEAB (ECLKOU1 cyc.) 0x4
* READ-To-WRITE (ECLKOU1 cyc.) 0x3
* READ-To-WRITE with Interrupt (BEx cyc.) 0x4
* WRITE-To-WRITE (ECLKOU1 cyc.) 0x2
* WRITE-To-DEAC/DEAB (ECLKOU1 cyc.) 0x4
* WRITE-To-READ (# of ECLKOU1 cyc.) 0x2
* Global Control Reg. (GBLCTL) 0x0005207C
* CE0 Space Control Reg. (CECTL0) 0xFFFFFFD3
* CE1 Space Control Reg. (CECTL1) 0x73A28E11
* CE2 Space Control Reg. (CECTL2) 0x73A28E11
* CE3 Space Control Reg. (CECTL3) 0x73A28E01
* SDRAM Control Reg.(SDCTL) 0x57115000
* SDRAM Timing Reg.(SDTIM) 0x005DC81B
* SDRAM Extended Reg.(SDEXT) 0x001FAF4D
* CE0 Space Secondary Control Reg. (CESEC0) 0x00000002
* CE1 Space Secondary Control Reg. (CESEC1) 0x00000002
* CE2 Space Secondary Control Reg. (CESEC2) 0x00000002
* CE3 Space Secondary Control Reg. (CESEC3) 0x00000002
*/
EMIFA_Config emifaCfg0 = {
0x0005207C, /*Global Control Reg. (GBLCTL) */
0xFFFFFFD3, /*CE0 Space Control Reg. (CECTL0) */
0x73A28E11, /*CE1 Space Control Reg. (CECTL1) */
0x73A28E11, /*CE2 Space Control Reg. (CECTL2) */
0x73A28E01, /*CE3 Space Control Reg. (CECTL3) */
0x57115000, /*SDRAM Control Reg.(SDCTL) */
0x005DC81B, /*SDRAM Timing Reg.(SDTIM) */
0x001FAF4D, /*SDRAM Extended Reg.(SDEXT) */
0x00000002, /*CE0 Space Secondary Control Reg. (CESEC0)*/
0x00000002, /*CE1 Space Secondary Control Reg. (CESEC1)*/
0x00000002, /*CE2 Space Secondary Control Reg. (CESEC2)*/
0x00000002 /*CE3 Space Secondary Control Reg. (CESEC3)*/
};
/*Handles*/
/*
*======== cslCfgInit() ========
*/
void cslCfgInit()
{
}
错误提示：
"D:\CCS3\C6000\cgtools\bin\cl6x" -g -q -o3 -fr"D:/CCS3/MyProjects/OSDmpeg4_Lyang_08_0523/obj/" -i"D:/CCS3/MyProjects/OSDmpeg4_Lyang_08_0523/include" -d"_DEBUG" -d"_PAL" -d"CHIP_DM642" -d"C6000" -mt -ml3 -mv6400 -@"Debug.lkf" "mpeg2_encodercfg_csl.c"
"mpeg2_encodercfg_csl.c", line 10: fatal error: #error "Please read the comment below to finish updating your project"
1 fatal error detected in the compilation of "mpeg2_encodercfg_csl.c".
Compilation terminated. 你确定你这是工程 我是看不懂了 连个模块都没有
这是什么语言编的啊 nios工程？我不懂~~ C语言写的，这是在DM642上移植MPEG-4源代码中的一个文件"mpeg2_encodercfg_csl.c"，其他编译都通过了，就这有一个error 不好意思 弄错了 楼主，应该发错了 看不懂~
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