二进制转BCD码的VHDL程序
把一个二进制数转换成7个4位BCD码（二进制数大小合适），怎样编写VHDL程序？比如把“1010 1010”（二进制）转换成“0000 0000 0000 0000 0001 0111 0000”（BCD） 回复 1# 小泡泡
仅供参考
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity B_BCD is
port(clk:in std_logic;
din:in std_logic_vector(26 downto 0);
y0,y1,y2,y3,y4,y5,y6,y7:out std_logic_vector(3 downto 0));
end B_BCD;
architecture behav of B_BCD is
type state is (s0,s1,s2);
signal present_state:state;
signal mid_in:std_logic_vector(26 downto 0);
signal d0,d1,d2,d3,d4,d5,d6,d7:std_logic_vector(3 downto 0);
begin
process(clk)is
begin
if clk‘event and clk=‘1‘ then
mid_in<=din;
present_state<=s0;
case (present_state) is
when s0=>
d0<=“0000“;d1<=“0000“;d2<=“0000“;d3<=“0000“;d4<=“0000“;d5<=“0000“;d6<=“0000“;d7<=“0000“;
present_state<=s1;
when s1=>
if mid_in>=“100110001001011010000000“ then mid_in<=mid_in-“100110001001011010000000“;
d7<=d7+1;
present_state<=s1;
elsif mid_in>=“000011110100001001000000“ thenmid_in<=mid_in-“000011110100001001000000“;
d6<=d6+1;
present_state<=s1;
elsif mid_in>=“000000011000011010100000“ thenmid_in<=mid_in-“000000011000011010100000“;
d5<=d5+1;
present_state<=s1;
elsif mid_in>=“000000000010011100010000“ thenmid_in<=mid_in-“000000000010011100010000“;
d4<=d4+1;
present_state<=s1;
elsif mid_in>=“000000000000001111101000“ thenmid_in<=mid_in-“000000000000001111101000“;
d3<=d3+1;
present_state<=s1;
elsif mid_in>=“000000000000000001100100“ thenmid_in<=mid_in-“000000000000000001100100“;
d2<=d2+1;
present_state<=s1;
elsif mid_in>=“000000000000000000001010“ thenmid_in<=mid_in-“000000000000000000001010“;
d1<=d1+1;
present_state<=s1;
elsif mid_in>=“000000000000000000000001“ then
m 好像没写完 用VERILOG好像没那么长吧
页:
[1]
