陈飞龙 发表于 2017-10-29 17:48:02

Altera推荐的寄存器的写法

Verilog Register with High Power-Up Value

reg q = 1’b1; //q has a default value of ‘1’
always @ (posedge clk)
begin
q <= d;
end

陈飞龙 发表于 2017-10-29 17:48:35

直接不需要复位端口，在定义变量时直接赋值:)

陈飞龙 发表于 2017-10-29 17:48:59

VHDL Register with High Power-Up Level
SIGNAL q : STD_LOGIC := '1'; -- q has a default value of '1'
PROCESS (clk, reset)
BEGIN
IF (rising_edge(clk)) THEN
q <= d;
END IF;
END PROCESS;

芙蓉王 发表于 2017-10-30 09:25:12

Altera推荐的寄存器的写法

zhangyukun 发表于 2017-10-30 09:27:42

Altera推荐的寄存器的写法

zxopenljx 发表于 2025-1-7 15:40:36

Altera推荐的寄存器的写法
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