跪求VHDL高手啊
我编的是一个时钟秒钟的设置敏感信号有时钟，上设置键，下设置键
一开始我全部弄在一个process里面
就是如果在set状态，(upset'event and upset='0')秒钟自动加1，(downset'event and downset='0')秒钟自动减1，正常情况下(clk'event and clk='1')秒钟自动加1
结果报错，说一个process里面不能有2个以上的边沿触发；
如果我改写了，将上述3个边沿触发放在了3个process里面，结果报错，不能有2个以上并行的process对同一个信号进行赋值；
再然后我就设置了一个变量，先3个process对变量赋值，变量再给信号赋值，结果报错说不能在process外定义变量。
上次提问了一次，最后还是没有解决问题，现在仿真错误，程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity second is
port
(clk0,clk,reset,setsecond,upset,downset:in std_logic;
enmin:out std_logic;
dh:buffer std_logic_vector (3 downto 0);
dl:buffer std_logic_vector (3 downto 0));
end;
architecture action of second is
signal upset_r,downset_r:std_logic:='1';
begin
process(reset,clk,setsecond,upset,downset,dh,dl,upset_r,downset_r)
begin
if reset='0' then
dh<="0000";
dl<="0000";
elsif setsecond='1' then
if (upset_r='1' and upset='0') then
if dl=9 then
dl<="0000";
if dh>=5 then
dh<="0000";
else
dh<=dh+1;
end if;
else
dl<=dl+1;
end if;
elsif (downset_r='1' and downset='0') then
if dl=0 then
dl<="1001";
if dh=0 then
dh<="0101";
else
dh<=dh-1;
end if;
else
dl<=dl-1;
end if;
end if;
else
if dl="1001" and dh="0101" then
enmin<='0';
else
enmin<='1';
end if;
if (clk'event and clk='1') then
if dl=9 then
dl<="0000";
if dh>=5 then
dh<="0000";
else
dh<=dh+1;
end if;
else
dl<=dl+1;
end if;
end if;
end if;
end process;
process(clk0)
begin
if (clk0'event and clk0='1') then
upset_r<=upset;
downset_r<=downset;
end if;
end process;
end;
upset和downset的时候还是出错。clk0是200Hz信号，clk是1Hz的信号。 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity second is
port
(clk:in std_logic;--200HZ
reset,setsecond,upset,downset:in std_logic;
enmin: out std_logic;
dh:out std_logic_vector (2 downto 0);--0~5,not need (3 downto 0)
dl:out std_logic_vector (3 downto 0));
end;
architecture action of second is
signal clk0:std_logic;--1HZ;
signal clk1:std_logic;--1hz;
signal clk_p:std_logic;--rising clk
signal setsecond_p:std_logic;
signal upset1,upset2:std_logic;
signal upset_p:std_logic;
signal downset1,downset2:std_logic;
signal downset_p:std_logic;
signal step:std_logic_vector(3 downto 0);
begin
process(clk)
constant min:integer:=99;
variable i:integer range 0 to min;
begin
if(clk'event and clk='1')then
if(i>=min)then
i:=0;
clk0<=not clk0;
else
i:=i+1;
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1')then
clk1<=clk0;
end if;
end process;
clk_p<=clk0 and(not clk1);
process(clk)
begin
if(clk'event and clk='1')then
setsecond_p<=setsecond;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1')then
upset1<=upset;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1')then
upset2<=upset1;
end if;
end process;
upset_p<=upset1 and(not upset2);
process(clk)
begin
if(clk'event and clk='1')then
downset1<=downset;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1')then
downset2<=downset1;
end if;
end process;
downset_p<=downset1 and(not downset2);
process(clk,reset)
constant idle: std_logic_vector(3 downto 0):="0001";
constant data_up: std_logic_vector(3 downto 0):="0010";
constant data_down: std_logic_vector(3 downto 0):="0100";
constant data_auto_up: std_logic_vector(3 downto 0):="1000";
variable h:std_logic_vector(2 downto 0);
variable l:std_logic_vector(3 downto 0);
begin
if(reset='1')then
enmin<='0';
h:=(others=>'0');
l:=(others=>'0');
step<=idle;
elsif(clk'event and clk='1')then
case step is
when idle=>
enmin<='0';
if(setsecond_p='1')then
if(upset_p='1')then
step<=data_up;
elsif(downset_p='1')then
step<=data_down;
else
step<=idle;
end if;
else
if(clk_p='1')then
step<=data_auto_up;
else
step<=idle;
end if;
end if;
when data_up=>
step<=idle;
if(l<9)then
l:=l+1;
enmin<='0';
elsif(l>=9)then
l:=(others=>'0');
if(h>=5)then
h:=(others=>'0');
enmin<='1';
elsif(h<5)then
h:=h+1;
enmin<='0';
end if;
end if;
when data_auto_up=>
step<=idle;
if(l<9)then
l:=l+1;
enmin<='0';
elsif(l>=9)then
l:=(others=>'0');
if(h>=5)then
h:=(others=>'0');
enmin<='1';
elsif(h<5)then
h:=h+1;
enmin<='0';
end if;
end if;
when data_down=>
step<=idle;
if(l>0)then
l:=l-1;
enmin<='0';
elsif(l=0)then
l:="1001";--9
if(h>=1)then
h:=h-1;
enmin<='0';
elsif(h=0)then
h:="101";--5
enmin<='1';
end if;
end if;
when others=>
enmin<='0';
h:=(others=>'0');
l:=(others=>'0');
step<=idle;
end case;
end if;
dh<=h;
dl<=l;
end process;
end;
看你真可怜，故花几分钟给你写了代码。
里面没有所谓的1HZ时钟信号输入，因为它完全可以由200HZ信号派生。你的buffer std_logic_vector 信号输出我直接改成了out std_logic_vector 。因为用buffer信号有很多讲究。还有就是你的dh输出是0~5，用std_logic_vector (2 downto 0)就足够了，没必要用std_logic_vector (3 downto 0)。这里面我没加消抖按键处理，有空就自己加上吧。
页:
[1]
