Falcon-E25TG型FPGA开发平台 ISE流程实验手册
Version 3.1，2011年11月Falcon-E25TG型FPGA开发平台
ISE流程实验手册
实验1：Xilinx ISE工具流程实验 p02-p14
实验2：Architecture Wizard与引脚分配实验 p15-p27
实验3：全局时序约束实验 p28-p40
实验4：综合技术实验 p41-p49
实验5：IP核生成器系统实验 p50-p57
实验6：Chipscope调试实验 p58-p69
实验1： Xilinx ISE工具流程实验
目标板：Falcon-E25TG
介绍
通过示例程序介绍ISE™ 工具的基本使用流程。
本实验适合于用户在学习完ISE工具设计流程和PicoBlaze微控制器的原理后，对所学知识进行理解验证。
目标
在完成示例实验后， 你将具备以下能力：
创建一个新工程
熟悉 FPGA 设计基本流程
掌握PicoBlaze基本技术特点
实验准备
1. 将光盘中Labs-materials / ISE-Flows文件夹拷贝到D:盘根目录下。或者将光盘Labs-materials目录下的ISE_Flows.rar直接解压缩到D:盘根目录下。
2. 通过下载电缆将计算机并口及Falcon-E25TG实验板的JTAG接口连接好。
3. 将RS232串口线一端与计算机连接好，另一端与Falcon-E25TG的RS232端口相连。
注意：下面各实验中，均按此准备。
步骤
实验1主要通过以下四步完成：
创建一个新工程
为工程添加源程序文件
对设计进行仿真（Simulation）
对设计进行实现（Implementation）
在实验手册的指导下，你将一步步地完成整个实验。
如果你已经熟悉ISE软件设计流程，则可以跳过一步步的详细说明，自行完成实验。
注意： 符号引导的段落是对该段落下面各个步骤的说明，不是操作步骤。
讲义中需要用户进行操作的所有步骤均由小写阿拉伯数字引导。
步骤1：开始
查看8位微控制器PicoBlaze 文档，熟悉其结构和指令集。本实验使用PicoBlaze中断应用作为ISE设计流程用例，有必要学习PicoBlaze结构和指令集，但不是必须的。
PicoBlaze用户手册KCPSM3_manual.pdf存放在D:\ ISE-Flows \ labs \ lab1 \ verilog（或vhdl）\ KCPSM3 \ docs\ 目录中。
打开 ISE Project Navigator，创建一个新的工程。
1. 选择“开始 →程序 → Xilinx ISE Design suite 12.4→ ISE Design Tools→ Project Navigator”（或者直接双击桌面Xilinx ISE Design suite 12.4 图标），启动ISE Project Navigator。
2. 在 Project Navigator界面中，选择File → New Project 菜单或者直接选择做上部分 图标，打开New Project Wizard （新工程向导） （图 1-1）。
3. 通过 “…” 按钮浏览下面的目录，然后点击 <OK>。
Verilog 使用者： D:\ ISE-Flows \ labs \ lab1 \ Verilog
VHDL 使用者： D:\ ISE-Flows \ labs\ lab1 \ VHDL
图 1-1. 新建工程向导
4. 在Name下面，输入Flow_Lab 。
5. 点击Next 。
6. 出现 Device Properties 对话框 （如图 1-2）。
图 1-2. Device Properties对话框
7. 选择下面的选项后，点击 Next ：
Device Family：Spartan3E
Device：XC3S250E
Package：TQ144
Speed Grade：–4
Synthesis Tool：XST（VHDL/Verilog）
Simulator：ISE Simulator （VHDL/Verilog）
Preferred Language：Verilog 或者 VHDL（选择你使用的语言）
8. 出现如下图所示对话框，点击Finish （图 1-3）。
图1-3. Project Summary对话框
添加 HDL源文件到工程。
9. 点击Project –Add Copy of Source或者点击右边工具栏，浏览到D:\ ISE-Flows \ labs \ lab1 \ VHDL（或Verilog）\ KCPSM3 \VHDL（或Verilog）文件夹。
10. 选择 VHDL或者Verilog 文件夹下的 kcpsm3_int_test 和 kcpsm3 文件，点击Open。
11. 点击 Next ，点击Finish。下面的对话框（图1-4）出现，表明你选择正确。
12. 点击OK ，接受默认设置。
图1-4. Adding Source Files对话框
图1-5. Project Navigator中的Sources窗口
注意： 图1-5中program - int_test 模块前有一红色的小问号。这是因为顶层文件kcpsm3_int_test.vhd/v 包含了 int_test.vhd/v模块的例化语句，而该模块又还没有添加到当前工程中。int_test.vhd/v模块用于生成PicoBlaze的指令存储器ROM（使用1个BlockRAM生成的ROM）。步骤2将讨论指令存储器ROM的生成。
步骤 2：生成指令存储器
本实验中，PicoBlaze的汇编应用程序已经写好，存储在int_test.psm文件中（注意：学习这个程序有助于对实验的理解）。使用PicoBlaze自带的汇编器汇编这个文件，将产生int_test.vhd文件、int_test.v文件和int_test.coe等指令存储器输出文件。根据使用的语言选择前两个文件中的一个例化到当前设计顶层文件（kcpsm3_int_test）中，综合工具能够自动推择（Infer）出PicoBlaze指令存储器（由1个BlockRAM生成的ROM）。另外，利用第三个文件int_test.coe，通过CoreGenerator工具也可以例化出PicoBlaze指令存储器。
1. 打开Windows浏览器，浏览到D:\ ISE-Flows \ labs \ lab1 \ VHDL （或Verilog ）\ KCPSM3 \ Assembler文件夹。
注意： KCPSM3.exe汇编工具、3个ROM_form模板文件，以及两个.psm汇编源文件都在此目录中（图 1- 6）。汇编完成后，所有输出文件也在这目录中出现。
图 1-6. 汇编目录内容
2. 使用文本编辑器打开int_test.psm 文件。参考（ug129）PicoBlaze 8-bit Embedded Microcontroller User Guide 和KCPSM3 manual ，理解源程序。（这些参考文档在D:\ ISE-Flows \ labs \ lab1 \ VHDL （或Verilog ）\ KCPSM3 \ Docs子目录中）
3. 打开DOS命令窗口。（“开始 程序 Xilinx design suite 12.4 accessoriesCommand Prompt”）
4. 使用cd 命令浏览到 Assembler 目录 （如图 1-7）。
D:\ ISE-Flows \ labs \ lab1 \ vhdl\KCPSM3\Assembler
或D:\ ISE-Flows \ labs \ lab1 \ verilog\KCPSM3\Assembler
图 1-7. Command Window
5. 在命令提示符下面输入汇编代码（图1-7），将自动产生指令存储器输出文件。
> kcpsm3 int_test.psm
注意： 此时在当前目录下可以看到init_test.vhd（用于生成指令存储器的VHDL语言程序） 、int_test.v（用于生成指令存储器的Verilog语言程序） 和init_test.coe（用于CoreGenerator工具生成指令存储器的初始化数据文件）等文件。其实，这三个文件中存储的都是应用程序汇编后产生的机器码，用户可以打开这三个文件，查看其中的二进制机器码部分。
6. 在 ISE Project Navigator中， Project Add Copy of Source 在目录路径D: \ ISE-Flows \ labs \ lab1 \ vhdl \KCPSM3 \ Assembler中找到 int_test.vhd 或int_test.v文件。（图1-8）
图 1-8. 添加 int_test.vhd文件到当前工程
7. 点击Open ，然后点击OK。这样，我们把 init_test.vhd或者init_test.v文件添加到当前工程中。（图 1- 9）
图1-9. PicoBlaze 设计的分层视图
注意：顶层文件 kcpsm3_int_test.vhd/v 包含了 int_test.vhd/v模块的例化语句。因此，在把源代码 int_test.vhd/v 添加到当前工程后，program模块前的红色小问号消失，即program模块在当前工程中不再是“空盒子”了。（如图1-9）
步骤3：行为仿真
在步骤3中，用户添加 testbench.vhd/.v 代码到当前工程中，使用Xilinx ISIM 仿真器完成行为仿真( behavioral simulation)，并检查仿真结果。testbench.vhd/.v代码是仿真测试台文件，描述了对欲测试模块的输入激励的产生和输出结果的处理，不能用于综合实现。在本实验中，testbench.vhd/.v文件已经写好，可以直接使用。在用户自己的设计中，需要自行编写此文件。
1. 在ISE Project Navigator，点击Project Add Copy of Source，指向D:\ ISE-Flows \ labs \ lab1 \ VHDL（或Verilog） \ KCPSM3 \ VHDL（或Verilog）目录。
2. 选择 test_bench.vhd 或者 testbench.v文件，点击Open。
图1-10. 选择 test_bench.vhd （或者testbench.v） 文件
3. 如图1-10，点击OK， test bench.vhd 文件被添加到当前工程中。
4. 如图1-11，选择View窗口中设置为Simulation。
图1-11. 包含Test Bench的Sources窗口
5. 如图1-12，单击Sourcese窗口中的test_bench.vhd/v，在Processes窗口中显示Xilinx ISE Simulator 工具栏。点击该工具栏前面的加号，右键单击Simulator Behavioral Model，选择Properties，打开属性对话框。如图1-13，在Simulation Run Time处输入10000ns，单击OK按钮，关闭属性对话框。
图1-12. 在Processes窗口中显示Xilinx ISE Simulator 工具栏
图1-13. 设置仿真属性
6. 双击Simulate Behavioral Model，对设计进行行为仿真。点击窗口放大图标，选择波形窗口中的名称栏，右键选择Radix—Hexadecimal，将会看到三个中断脉冲及其中断值，仿真结果波形如下图所示（图1-14）。
图1-14. ISIM 行为仿真结果
7. 利用工具栏中的放大工具放大仿真结果图形，确认仿真结果正确。
注意：在D: \ ISE-Flows \ labs\ lab1 \ vhdl \ KCPSM3 \ Assembler目录下，文件 int_test.log中记录了每一条指令在指令存储器中的地址和机器码，用户可以对照此文件验证仿真结果的正确性。
8. 关闭仿真窗口，结束仿真。
步骤 4：设计的实现
步骤4对设计进行实现。
1. 如图1-15，在工程的Sources窗口，选择Implementation，并单击工程的顶层文件kcpsm3_int_test.vhd/v。
图 1-15. Sources 窗口
2. 如图1-16所示，在Processes窗口中，双击Implement Design。
图 1-16. Processes for Source窗口
3. 展开Implement Desig前的加号，会看到实现的三个步骤。每个步骤运行完成后，步骤前面会显示一个小图标，表示该步骤的完成情况。图标示意如下：
表示该操作步骤成功完成
表示该操作步骤虽完成但有警告信息
表示该操作步骤因错误而未完成
注意：在实现过程中，Project Navigator 底部的消息窗口会实时显示实现过程产生的各种消息。
4. 每个操作步骤完成后，会生成相应的报告，报告中包含步骤运行过程中产生的详细信息。这些报告可以在ISE Project Navigator 中Design Summary窗口中的Detailed Reports部分直接访问，也可以在Processes窗口中各个步骤下通过点击相应命令访问。如图1-17、1-18、1-19所示。
图1-17. Design Summary 窗口总体信息
图1-18. Design Summary 窗口中的资源利用信息
图 1-19. 在Design Summary窗口中的Detailed Reports部分访问各种报告
结论
在实验1中，我们完成了ISE设计的主要步骤：创建一个工程、添加源文件、仿真设计和设计实现。
在实验2中，我们将学习查看各种设计报告，分析设计，检查设计的面积和性能指标是否满足要求。
实验2：Architecture Wizard与引脚分配实验
目标板：Falcon-E25TG
介绍
介绍结构向导和PlanAhead的引脚分配工具及其应用。
目标
完成这个实验后，你将能够：
1. 使用结构向导配置一个DCM组件
2. 例化DCM组件到设计中
3. 使用PlanAhead分配管脚位置
4. 执行设计确认管脚分配
5. 下载到硬件中测试
设计概览
实验2利用UART实时时钟（ Real-Time Clock）模块在Falcon-E25TG板上完成一个可以通过超级终端查看和设置时间的带有闹钟功能的实时时钟系统。UART实时时钟模块及其使用文档可以在免费的PicoBlaze发行包中找到。
本系统设计实现了带有小时、分和秒的实时时钟，并且具有设置闹钟的能力。系统利用超级终端软件通过UART串行通信口设置、查看时间信息和闹钟信息。
实验中将利用一些简单的ASCII命令。当超级终端窗口中“KCPSM3>” 提示符显示的时候，可以通过键盘向开发板系统发送操作命令。错误的操作命令将在超级终端上出现“syntax error”消息，错误的时间设置将出现“Invalid Time” 消息。如果命令传输比设计的处理速度快（比如接受缓存器存满），“overflow error” 消息将出现（当然，这种情况不大可能发生） 。
系统需要55 MHz 的工作时钟。因为Falcon-E25TG板只提供50 MHz的时钟，所以需要使用结构向导（Architecture Wizard）来例化DCM模块，输出55 MHz工作时钟。
步骤
本例主要由四部分组成：
1. 使用结构向导配置DCM；
2. 例化DCM到VHDL/Verilog 设计中；
3. 分配管脚位置；
4. 实现设计，下载设计，通过开发板验证设计。
在实验手册的指导下，你将一步步地完成整个实验。
如果你已经熟悉ISE软件设计流程，则可以跳过一步步的详细说明，自行完成实验。
注意： 符号引导的段落是对该段落下面各个步骤的说明，不是操作步骤。
讲义中需要用户进行操作的所有步骤均由小写阿拉伯数字引导。
步骤 1：使用结构向导Architecture Wizard来配置 DCM
打开存在的工程。
1. 选择 开始→ 所有程序 → Xilinx ISE Design Suite12.4→ISE Design Tools → Project Navigator，进入ISE的Project Navigator环境；
2. 选择File → Open Project，并指向如下目录，选择arwz_pace.xise打开工程；
Verilog users: D:\ISE_FLOWS\ labs\ lab2\verilog\arwz_pace
VHDL users: D:\ISE_FLOWS\ labs\ lab2\vhdl\arwz_pace
该设计还没有例化DCM模块。下面的步骤使用结构向导配置一个输入时钟为50MHz，输出时钟为55MHz 的DCM。
1. 选择Project New Source。
2. 在打开的 Source窗口中， 选择 IP (CoreGen & Architecture Wizard) 并且输入 my_dcm 作为文件名。
图2-1 选择 IP (CoreGen & Architecture Wizard)
3. 点击 Next。
4. 在选择IP类型窗口中展开 FPGA Features and Design Clocking Spartan-3E， Spartan-3A ，选择Single DCM SP v12.1i 。(图2-2)
图 2-2. Architecture Wizard选择框
5. 点击 Next， 然后点击 Finish。
6. 在 Xilinx Clocking Wizard – General Setup 窗口中 ，设置如下选项 (图2-3)：
CLK0、CLKFX和 LOCKED：选择
RST box：不选择
Input Clock Frequency：填入50 MHz
图2-3 Xilinx Clocking Wizard – General Setup窗口
注意: 在Clocking Wizard 中指出输入频率，结构向导将自动配置DCM的工作模式（高频模式或低频模式）。基于输入的时钟频率，结构向导可以计算出要求的输出频率是否在允许的范围内。另外，如果选用了CLKFX输出，结构向导也会计算CLKFX输出频率大小并估计时钟抖动情况。
7. 点击Next。
8. 在Xilinx Clocking Wizard – Clock Buffers 窗口中 (图 2-4)， 选择默认值点击Next。
图2-4 Xilinx Clocking Wizard – Clock Buffers窗口
9. 在Xilinx Clocking Wizard – Clocking Frequency Synthesizer对话框的Use output frequency下填入55MHz。(图 2-5)
图2-5 指定DCM输出频率
10. 单击finish按钮，可以在工程的Sources窗口中看到my_dcm.xaw添加到当前工程中，但没有加入到顶层设计模块的文件层次中，需要下一步的例化（如图2-6）。
注意：如果此时还没有在当前工程的Sources窗口中看到my_dcm.xaw ，可以通过Project Add Source手动添加。 (图2-6)
图2-6 在设计层次中列出了DCM
步骤2a：例化DCM到Verilog设计中
注意：VHDL用户跳过此步，直接参考步骤2b
当前工程需要的所有必要文件均已经创建，步骤2a将在顶层设计中例化DCM模块。实验2通过复制例化模板中相关内容，然后粘贴到顶层设计中的方式完成例化。
1. 在 Sources 窗口中， 双击uart_clock.v 打开源代码。
2. 在Sources窗口中，选择my_dcm.xaw。在Processes窗口中双击View HDL Instantiation Template，则my_dcm模块的例化模板在右面的编辑器中打开。在例化模板（文件形式my_dcm.tfi）中，拷贝元件声明部分（在// Instantiate the module注释下），粘贴到uart_clock.v代码中的// Insert DCM component here 注释下面；
3. 实验中的my_dcm端口连接信号没有采用系统默认名字，需要对my_dcm端口连接信号进行修改，具体修改请参照下面的代码（也可把下面的代码拷贝并粘贴到uart_clock.v代码中的// Insert DCM component here注释的下方）。
my_dcm inst_my_dcm (
CLKIN_IN(clk),
CLKFX_OUT(clk55MHz),
CLKIN_IBUFG_OUT(),
CLK0_OUT(),
LOCKED_OUT(lock) );
4. 在注释//Signals for DCM 下，定义DCM的55MHz输出连接信号：
wire clk55MHz;
注意：此时，uart_clock.v设计已经更新，所有的时钟信号已经被重新命名成新的时钟(clk55MHz)。
5. 在顶层实体中添加lock输出端口：
module uart_clock (tx, rx, alarm, clk, lock)
output tx;
input rx;
output alarm;
input clk;
output lock;
注意：lock输出端口将驱动 Falcon-E25TG板的LD0灯。硬件调试时，LD0灯亮，表明DCM已经成功实现时钟锁定。
6. 点击File→Save 保存文件。此时，模块my_dcm.xaw已经插入到顶层设计模块文件层次的正确位置。（图2-7）
步骤2 b：例化DCM到VHDL设计中
注意：Verilog用户跳过此步!
当前工程需要的所有必要文件均已经创建，步骤2b将在顶层设计中例化DCM模块。实验2通过复制例化模板中相关内容，然后粘贴到顶层设计中的方式完成例化。
1. 在 Sources 工程窗口中， 双击 uart_clock.vhd打开源代码。
2. 在工程的Sources窗口中，选择my_dcm.xaw，在Processes窗口双击View HDL Instantiation Template，例化模板文件（my_dcm.vhi）被打开。在HDL例化模板文件中，拷贝元件声明（从COMPONENT my_dcm 到END COMPONENT）并粘贴到uart_clock.vhd代码中注释语句-- Insert DCM component declaration here下方；
3. 按照下面代码修改端口连接信号，或者将下面代码拷贝并粘贴到uart_clock.vhd代码中的注释语句-- Insert DCM component instantiation here下方）。
Inst_my_dcm: my_dcm
PORT MAP(
CLKIN_IN => clk，
CLKFX_OUT => clk55MHz，
CLKIN_IBUFG_OUT => open，
CLK0_OUT => open，
LOCKED_OUT=> lock );
4. 在注释语句--Signals for DCM 下面，定义DCM的55 MHz输出连接信号：
signal clk55MHz : std_logic;
注意: uart_clock.vhd设计已经更新。所有的时钟信号已经被重新命名成新的时钟(clk55MHz)。
5. 在顶层实体中添加lock输出端口：
entity uart_clock is
Port (
tx : out std_logic;
rx : in std_logic;
alarm : out std_logic;
clk : in std_logic;
lock : out std_logic );
end uart_clock;
注意: lock输出端口将驱动 Falcon-E25TG板的LD0灯。硬件调试时，LD0灯亮，表明DCM已经成功实现时钟锁定。
6. 点击 File→Save，保存文件。此时，模块my_dcm.xaw已经插入到顶层设计模块文件层次的正确位置。（图2-7）
图 2-7. 例化完成后的设计文件层次图
步骤 3：分配管脚位置
步骤1和步骤2完成了添加DCM模块的设计。在进行设计实现之前，需要对FPGA的输入和输出端口进行管脚位置分配。在这一步骤中你将使用PlanAhead工具进行管脚分配。
1. 在工程的Hierarchy窗口中，选择顶层设计文件uart_clock.vhd/.v 。
2. 在工程的Processes窗口中，展开User Constraints，双击 IO-Pin Planning(PlanAhead)-Pre-Synthesis 以打开PlanAhead。
注意：当问是否添加UCF文件到工程，点击“yes”。
3. 如果出现介绍窗口，点击CLOSE关闭。
注意：对于VHDL用户来说，可能会报告显示8个错误，忽略他们因为他们并不是由设计生产的。
4. 在I/O Ports窗口中选择clk信号，在I/O Ports Properties窗口中的位置框中键入p54 然后点击Apply。选择configure选项，然后选择LVCMOS33作为接口标准。其他号按类似方法进行（参考D:\ISE_FLOWS \ ucf文件夹下lab2_ucf.txt文件，I/O端口对应的FPGA管脚位置出现在“LOC =”后面）。如图2-8所示（配置好管脚的约束视图）。
Clk： 连接开发板上的50MHz晶振
Lock： 连接开发板上的LD0灯
Alarm：连接开发板上的LD1灯
Rx： 连接开发板上的MAX3232芯片的串行数据接收管脚
Tx： 连接开发板上的MAX3232芯片的串行数据发送管脚
图 2-8：管脚约束视图
5. 在I/O Ports窗口中选择一个引脚（例如clk），点击Fit Selection按钮，会显示出所选引脚的器件和封装视图，如图2-9所示。
6. 点击File-Save Design来保存引脚分配。
7. 点击File-Exit退出Planhead，点击OK。
图 2-9. 器件和封装视图
8. 单击Sources窗口中的uart_clock文件，在Processes窗口中展开User Constraints ，双击 Edit Constraints (Text)，观察通过PlanAhead在uart_clock.ucf中生成的约束文件。观察UCF 文件的的文本内容，确认管脚分配已经正确写到约束文件中。观察到UCF文件存在在路径名上存在错误，修改如图2.10和2.11所示。
图2.10 修改前
图2.11 修改后
步骤 4：查看运行报告并设置超级终端
实现设计，查看报告报告，确认管脚分配符合要求。设置超级终端。
1. 在当前工程的Sources窗口中，选择顶层设计文件uart_clock.vhd/.v 。
2. 在当前工程的Processes 窗口中，展开Implement Design ，然后展开Place & Route ，展开Back-Annotate Pin Locations。
3. 双击 View Locked Pin Constraints （Project Navigator自动决定需要运行哪些程序，这些程序运行完成后，报告被打开） 。
4. 查看运行报告，查看步骤3中完成的管脚分配是否正确实现。
5. 打开超级终端。步骤是： 开始程序附件通信超级终端。
6. 为超级终端取一个名字，点击OK。指定COM1为端口连接。
7. 为端口设置下面的参数。然后点击 确定完成设置（如图2-12）。
每秒位数： 38400
数据位：8
奇偶校验：无
停止位：1
数据流控制：无
图 2-12. 串行端口通信设置
8. 在超级终端窗口中选择文件菜单，点击 属性 按纽，选择设置，点击ASCII码设置，选中复选框将换行符附加到传入行末尾（图2-13）。点击确认 完成属性设置。
图 2-13. 串行端口连接的ASCII设置
步骤 5：下载设计
产生下载比特流（bitstream）文件，并下载到FPGA中。
1. 为Falcon-E25TG开发板连接电源适配器、JTAG下载线和串行通信电缆，打开Falcon-E25TG开发板电源开关。
2. 选中顶层文件uart_clock.vhd/.v ，双击Generate Programming File ，产生可以下载到FPGA的bitstream文件。
3. 比特流文件产生完成后，展开Generate Programming File， 双击Manage Configuration Project (iMPACT)。
4. 点击Initialize Chain按钮，点YES，浏览到工程目录选择uart_clock.bit
图 2-14.分配了可配置文件的 JTAG 链
5. 在iMPACT 窗口中，右键点击xc3s250e ，选择Program ，在Programming Options 对话框中点击OK。配置比特流文件开始向FPGA下载，如果下载成功出现Program Succeeded。
注意：下载成功后，超级终端中出现KCPSM3>提示符。（如果没有出现KCPSM3>提示符，将光标移至超级终端内，按Backspace键即可）
图 2-15. 超级终端显示窗口
步骤6：运行URAT实时时钟
通过超级终端向系统发出命令，验证设计正确性。可以参考手册查看详细说明。（手册为UART_real_time_clock.pdf）
1. 在KCPSM3>提示符后输入“time”命令，回车后，超级终端中以hh:mm:ss格式显示当前时钟（如图2-16）；
图 2-16. 显示当前时间
2. 在命令提示符后输入“alarm”命令，则以hh:mm:ss形式显示当前设置的告警（alarm）时间。注意，此时alarm功能是关闭的（如图2-17）。
图 2-17. 显示闹铃时间和状态
3. 在命令提示符后输入“alarm on”命令，告警（alarm）功能开启。
4. 在命令提示符后输入“alarm 00:00:30”设定告警时间30秒后，输入“time 00:00:00”设定当前时间后，30秒后，板上的LD1灯点亮。
5. 在命令提示符后输入“alarm off”命令，LD1灯熄灭。
结论
本实验中，使用结构向导Architecture Wizard配置 DCM 模块，并例化到当前设计中。使用 PlanAhead分配IO端口的管脚位置。最后，实现并下载设计，在硬件中完成验证。
实验3：全局时序约束实验
目标板：Falcon-E25TG
介绍
实验3学习使用全局时序约束来提高设计的工作时钟频率。
实验3学习使用Post-Map Static Timing Report Post-Place 和Post-Place&Route Static Timing Report 分析设计性能。
目标
在完成实验后，你将能够：
使用Xilinx Constraints Editor 输入全局时序约束
观察 Post-Map Static Timing Report 确认时序约束的合理指标
对于每一个时序约束，使用 Post-Place and Route Static Timing Report 查看关键路径
设计概览
在Xilinx开发环境中，实现前输入的约束条件称为逻辑约束，逻辑约束保存在UCF文件中。用户可以直接创建和编辑UCF约束文件，但需要熟悉UCF文件的语法以及设计中各触发器、网络和PAD等元件的命名，而使用约束编辑器（Constraints Editor）来创建和修改约束，可以降低要求，提高效率。
实验3硬件设计原理如图3-1所示，是一个带有UART外设的PicoBlaze系统。
图 3-1. PicoBlaze 系统
这个实验的主要任务是用PicoBlaze汇编语言编程实现一个回路测试（loopback test）系统。回路测试系统首先发送一个信号到某设备，然后再从该设备返回信号，以测试该设备是否正常工作。
如图3-1所示，系统输入端口有：
clk 时钟信号（Falcon-E25TG开发板上的50Mhz振荡信号）
rst 复位信号
rs232_rx 串行输入
switches 8-bit 的开关输入
输出端口有：
rs232_tx 串行输出
leds 8-bit LED输出
实验3通过开发板上的LED灯接收开关发出的信号，拨动开关可以在相应的LED灯上看到其亮灭。另外，系统的UART TX模块向计算机发送数据，系统的UART RX模块接收计算机发回来的数据。
软件程序可以正确执行两个loopback 功能：在LED灯上响应开关的设置，RS232 串口接收端口响应发送端口的串行数据。
实验完成之后，你将能够理解怎样使用PicoBlaze 设计简单的嵌入式处理程序。
时序报告信息
时序报告详细说明了为什么时序约束失败，哪些路径是关键路径。
时序分析器（Timing Analyzer）产生时序报告。时序分析器界面包括三个窗口 (图 3-2)。
使用左边的分层浏览器（Hierarchical Browser）可以浏览报告的各个部分。
右边的路径细节（Path Detail）窗口包括时序报告的详细说明。
右边顶上的窗口显示在分层浏览器中选择的项目。该项目内容显示在Path Detail窗口中。
图 3-2. The Timing Analyzer GUI
路径细节窗口中 (图 3-3) 包括有关路径延迟的详细信息，其中包括：
Slack：约束值（也就是要求的路径延迟值）与实际路径延迟值的差值 (负数表明实际延迟大于约束值，即没有满足要求 )
路径的源点与终点
路径延迟的详细组成列表
延迟路径中每个网络的扇出（Fanout）
路径延迟总和
逻辑延迟和网络延迟的百分比例（这个值表示你的延迟路径是否合理 ）。
图 3-3. 详细的路径分析
步骤
实验3中，你将生成一个简单的嵌入式系统，并通过全局时序约束提高性能。主要步骤如下：
1. 汇编一个PicoBlaze工程。
2. 输入全局时序约束。
3. 输入引脚约束文件。
4. 实现设计，分析时序报告。
5. 编写软件，运行HDL仿真。
6. 硬件验证。
在实验手册的指导下，你将一步步地完成整个实验。如果你已经熟悉ISE软件设计流程，则可以跳过一步步的详细说明，自行完成实验。
注意： 符号引导的段落是对该段落下面各个步骤的说明，不是操作步骤。
讲义中需要用户进行操作的所有步骤均由小写阿拉伯数字引导。
步骤1：汇编程序模板
在 ISE Project Navigator中打开time_const 工程，汇编源程序program.psm，产生program.vhd/v文件，用于生成指令存储器。
1. 选择 开始→程序→Xilinx ISE Design Suite 12.4→ISE Design Tools→Project Navigator，进入ISE Project Navigator环境。
2. 选择File→Open Project，并指向如下目录，选择time_const.xise，打开工程；
Verilog 使用者: d:\ISE_Flows\ labs\ lab3\verilog\time_const
VHDL 使用者: d:\ISE_Flows\ labs\ lab3\vhdl\time_const
3. 选择 开始→程序→附件→命令提示符，打开DOS命令窗口，使用cd命令指向汇编编译器目录：
> cd d:\ISE_Flows \labs\lab3\verilog\Assembler (Verilog 使用者)
> cd d:\ISE_Flows\ labs\ lab3\vhdl\Assembler (vhdl 使用者)
4. 进入到Assembler目录后，在DOS命令提示符号>后输入：kcpsm3 program.psm命令。命令完成后，会在Assembler下生成一些文件，其中包括VHDL文件 (program.vhd) 和Verilog文件 (program.v)，这两个文件用于综合（综合出程序存储器ROM）和仿真。
5. 将program.vhd/v 文件添加到当前工程中。
6. 单击工程Sources窗口中的顶层文件loopback.vhd/v，然后双击Processes窗口中的Synthesis- XST目录下的Check Syntax，检查是否有语法错误。
7. 在Behavioral Simulation 模式中，使用testbench.v/vhd作为仿真测试平台进行仿真。时间为35000ns。
注意：放大仿真波形图后，可以看到类似下图的结果。十六进制55表示开关的输入信号，但在LED灯上没有输出。在后面的实验中，将编辑代码使LED灯响应开关设置。
图3-4 开关位置没有反映到LEDs上
步骤2：输入全局时序约束
步骤2使用约束编辑器输入周期（PERIOD）和偏置输入/输出（OFFSET IN/OUT）约束。
1. 在工程的Hierarchy窗口中，选择顶层文件 loopback.vhd/.v
2. 在Sources 窗口之下的Processes窗口中，展开User Constaraints，双击Create Tming Constraints (如图 3-5)。如果在当前工程目录中没有相关的约束文件，Project Navigator 将自动创建一个约束文件。
3. 点击 Yes 创造一个新的UCF文件：loopback.ucf，将其添加到工程中。
4. 打开约束编辑器，在constraint type下面选择clock domains(如图 3-6)。
图3-5 工程的Processes窗口
图3-6 全局时序约束编辑器
设置全局时钟信号clk的周期（Period）约束是20ns
5. 双击unconstraints clock下面的clk，打开Clock Period对话框。(图 3-7)
6. 点击OK，接受默认值（20ns）。
设置全局时钟信号clk的输入偏置约束（OFFSET IN）值为7ns，输出偏置约束（OFFSET OUT）值为7.5 ns 。保存约束，退出约束编辑器。
7. 选择constraint type窗口下面的inputs，双击unconstraint port列旁边的空白区域打开offset in wizard，保留默认设置选择next。(图 3-8)
8. 在如图3-9所示的空白区域输入7 ns 的约束值。点击 OK。（图 3-9）
9. 选择constraint type窗口下面的outputs，双击unconstraint port列旁边的空白区域打开offset in wizard，保留默认设置选择next。在如图3-10所示的空白区域中输入7.5 ns 的约束值。点击 OK。（图 3-10）
注意：上述约束条件均出现在约束编辑器左下角的窗口中。（图3-10 ）
图3-7 时钟周期对话框
图3-8 OFFSET IN Wizard – Clock Edge Page
图 3-9. OFFSET IN 约束对话框
图3-10. OFFSET OUT 约束对话框
步骤 3：输入引脚位置约束
步骤3为顶层设计I/O端口指定管脚位置。本例中通过直接复制给定文本文件中的管脚位置描述到UCF文件完成管脚分配。
1. 展开 User Constraints 双击 Edit Constraints （图 3-11） ，打开 UCF 文件。
图 3-11.打开 UCF 文件
2. 打开d:\ ISE_Flows \ lab3_ucf.txt文件。
图 3-12. 管脚位置约束
3. 复制lab3_ucf.txt文件中的约束到UCF文件中。
4. 保存并关闭 UCF 文件。
步骤 4：设计时序分析
实现（Implement）设计。查看 Post-Map Static Timing Report 和 Post-Place & Route Static Timing Report ，分析设计时序，并完成表1和表 2。
1. 在Processes 窗口中，展开 Implement Design ，进一步展开Map。
如果没有看到Implement Design ，请确认是否选择了Source 窗口中的loopback.vhd/.v 文件。
2. 展开 Generate Post-Map Static Timing 。
3. 双击Analyze Post-Map Static Timing ，打开静态时序分析工具（Timing Analyzer），查看Map后的时序情况。
使用Post-Map Static Timing Report检查本例中的时序约束是否可行，以避免浪费Place & Route时间。
在报告中找到CLKFX_BUF ( DCM的输出) 的PERIOD constraint，完成问题①。
如果Post-Map Static Timing Report中没有找到时序约束，右键单击Post-Map Static Timing Report 选择Rerun All 。
①问题-完成下表：
Chart 1 PERIOD constraint OFFSET IN constraint OFFSET OUT constraint
Constraint
Post-Map
4. 关闭Timing Analyzer 窗口。
5. 在Processes窗口中， 展开Place & Route 和Generate Post-Place & Route Static Timing 。
6. 双击 Post-Place & Route Static Timing Report，打开静态时序分析工具（Timing Analyzer），查看Place&Route后的时序情况，并完成问题②。
②问题-完成下表：
Chart 2 PERIOD constraint OFFSET IN constraint OFFSET OUT constraint
Constraint
Post-P&R
注意：如果设计在place & route后不满足时序要求，需要放宽约束重新实现。
步骤 5：编写程序执行HDL仿真
通过上面几个步骤的操作，硬件已满足时序要求。
步骤5开发PicoBlaze汇编程序满足软件要求。实验中已经给出应用程序模板，包括大量常数的定义。本实验中，用户只需要编写简单代码完成三个任务（Task），其中task ＃3最难。实验5只需要完成task ＃1，Task #1完成开关和灯的回路测试。
需要注意的是，每次改变代码后，必须重新进行汇编，以生成新的指令存储器。
1. 在Assembler 目录中找到program.psm，编写代码完成task #1，实现读取开关状态并写到LED灯控制端口。重新编译一次。
提示: 你仅需要写两行代码（参考 KCPSM3 用户手册）。如果不能顺利完成代码编写，可以参考LabSolutions中相应文件。
2. 转到 Behavioral Simulation 模式，双击Simulate Behavioral Model
3. 分析输出波形，完成后关闭仿真窗口。 （图3-13）
图3-13. LEDs响应开关的设置信号
注意: 二进制值 10101010 (十六进制aa) 出现在PicoBlaze 的Switches输入端口，经过一段延时后，又出现在LED灯输出端口上。仿真控制台（Sim Console）显示仿真成功信息。（图3-14）
图 3-14. 在 Simulation Console中观察信息
步骤6：产生Platform Flash PROM 文件
Falcon-E25TG实验板配置了Xilinx XCF02S/ XCF04S platform flash PROM。步骤6使用iMPACT工具产生 PROM编程比特流文件（Intel formatted MCS格式）。
1. 双击Processes窗口中的Generate Programming File ，产生FPGA下载比特流文件。
2. 启动iPACT工具，双击create PROM file ，按下图所示选择各个选项。(图3-15)
图3-15. 设置PROM文件格式
3. 点击 OK 和Finish，添加 loopback.bit 。当对话框出现，点击No。这样不再添加另外的FPGA比特流文件（1个PROM支持配置多片FPGA）。
4. 双击 Generate File…，产生PROM用比特流文件（MCS 文件），如果成功，能够看到“PROM File generation succeeded”消息。（图3-16）
图 3-16. 产生MCS 文件
步骤7：配置PROM，运行LoopBack实验
步骤7选择通过选择配置模式，分别对PROM和FPGA进行配置，并在开发板上测试loopback程序。
1. 将开发板配置模式选择开关置于JTAG模式，打开开发板电源。（参见Falcon-E25TG板手册）
2. 双击 Boundary-Scan 。图3-17所示。
图 3-17. 在 iMPACT中选择 Boundary Scan
3. 在iMPACT的 Boundary Scan窗口中，右键单击白色区域，选择Initialize Chain 。
4. 当询问xc3s250e的配置比特流文件时，点击Bypass。
5. 为xcf02s/04s Platform Flash添加 .mcs 文件。
6. 右键单击JTAG链中的xcf02s/04s，选择Program。出现Programming Properties 对话框时，点击OK>。
注意：如果program不成功，不选择Erase Before Programming选项，然后重新进行program。
7. 将开发板配置模式选择开关置于M-S模式，按压开发板的PROG按钮，或者重新上电，开发板将从PROM中配置FPGA。拨动开关，可以看到相应 LED灯的亮灭。
结论：
本实验使用Xilinx Constraints Editor 输入全局时序约束，通过查看Post-Map 和 Post-Place & Route Timing Report分析设计时序。
时序约束能够满足性能要求。实现工具第一次布局布线时，必须确定设计的时序约束是否可行。可以根据Post-Map Static Timing Report估计时序性能。通过查看Post-Place & Route Static Timing Report确定时序要求是否得到满足。
答案
答案并不唯一，具体结果和实验使用的软件版本、补丁版本以及操作系统等因素有关。
①问题-完成下表：
Chart 1 PERIOD constraint OFFSET IN constraint OFFSET OUT constraint
Constraint ~18.18 ns 7 ns 7.5 ns
Post-Map ~8.85 ns ~7.115ns ~3.76 ns
②问题-完成下表：
Chart 2 PERIOD constraint OFFSET IN constraint OFFSET OUT constraint
Constraint ~18.18 ns 7 ns 7.5 ns
Post-P&R ~13.78 ns ~6.89 ns ~4.54 ns
实验4：综合技术实验
目标板：Falcon-E25TG
介绍
综合是FPGA/CPLD设计流程中的重要环节，综合结果的优劣直接影响最终的布局布线结果。好的综合器能使用户的设计占用芯片物理面积最小，而工作频率最快，这是评定综合器优劣的重要指标。
Synplify/Synpliy Pro是Synplicity公司出品的综合工具，以综合速度快以及优化效果好备受关注。XST（Xilinx Synthesis Technology）是Xilinx公司在ISE软件中内嵌的综合工具，虽然它与Synplify/Synpliy Pro等业界流行的综合工具相比特点并不突出，功能也不全面，但是Xilinx对自己的FPGA/CPLD内部结构最为了解，因此XST对Xilinx器件的支持也最为直接有效。更重要的是，XST内嵌在ISE中，可以直接使用，不会再有其它的成本。
实验4介绍在Xilinx FPGA 设计流程中，通过使用XST综合选项（属性）获得更高性能。
目标：
在完成试验后，你将能够：
使用Keep Hierarchy和fanout 等综合选项改善综合结果，提高设计性能。
修改XST综合选项，阅读XST 综合报告，判断综合结果质量。
步骤：
本实验由以下四部分组成：
查看硬件并完成应用软件设计
按照综合选项默认值进行综合
改变综合选项
在RTL 中查看综合结果。
在实验手册的指导下，你将一步步地完成整个实验。如果你已经熟悉ISE软件设计流程，则可以跳过一步步的详细说明，自行完成实验。
注意： 符号引导的段落是对该段落下面各个步骤的说明，不是操作步骤。
讲义中需要用户进行操作的所有步骤均由小写阿拉伯数字引导。
步骤 1：查看设计硬件组成，完成应用软件
打开 ISE™ Project Navigator，打开工程文件synth_lab.ise.
1. 选择开始 →程序 → Xilinx ISE Design suite 12.4→ ISE Design Tools → Project Navigator，打开 Xilinx ISE 。
2. 选择 File → Open Project，选择synth_lab.xise，点击打开
Verilog 用户：D:\ISE_Flows\ labs\ lab4\verilog\synth_lab
VHDL用户：D:\ISE_Flows\ labs\ lab4\vhdl\synth_lab
更新实验3中的program.psm 文件，完成task #2（任务2在屏幕上显示“Xilinx Rules”字样），汇编后添加到当前工程。
3. 打开 program.psm （位于本实验的Assembler 子目录中），添加代码完成task #2。
提示：在程序的顶部，所有的 ASCII 字符以constants 的形式列出。只有两条指令（load 和output）来显示单个字符。如果编码存在困难，可以直接参考LabSolutions中的相应文件。
4. 打开命令窗口，浏览到Assembler 目录。该目录包含刚才编码的program.psm文件。
5. 在DOS提示符下输入下面的命令，汇编程序对应用程序program.psm进行汇编，生成的文件用于产生指令存储器。
> kcpsm3 program.psm
注意：如果program.v （或者 .vhd）文件已经在到当前工程中。可将其移除后，再将新生成的文件重新加载到工程中。
步骤 2：按照默认值进行综合和实现
对顶层文件 loopback.v/.vhd进行综合
1. 点击 loopback.v/.vhd
2. 在 Processes窗口中，双击Synthesize - XST
查看综合报告，并在Sources窗口中，回答问题①和②。
3. 在design overview窗口中，单击View Synthesis Report
4. 使用页面最下面的Find 工具 , 输入Timing Summary ，按Enter 键。
①写下估计的时钟频率（用于与后来结果比较）：
____________________________
5. 在Find中输入Device Utilization，点击Find Next。
②写下资源占用情况 ：
Slices
Slice Flip Flops
4 input LUTs
IOBs
BRAMs
Global Clocks
DCMs
6. 关闭综合报告。
7. 在process窗口中，展开Implement Design ，展开Place & Route。
双击Analyze Timing/FloorPlan Design (PlanAhead)，网表视图会被打开，通过Tools → Show Hierarchies可以观察loopback 和Primitives两个模块的层次关系（图4-1和图4－2）
8. 退出 planAhead。
图 4-1. Nets and Primitives视图
图 4-2. 物理层，网表和设计的平面视图
步骤3：改变综合选项
一般来说，HDL设计是各层次模块的集合。保持模块的层次结构或者将层次结构打平（Flattened），在某种程度上都有利于设计，需要具体问题具体分析。对FPGA而言，如果能够注意同步设计技巧，则选择保持设计的层次结构更能提高性能，便于调试分析。而在某些情况下，尤其是非同步电路设计中，打平设计的层次结构可以让综合工具对设计进行更好的优化。
有时候，按照默认值综合出来的效果并不好。需要设计者理解常用的综合选项，灵活应用。
改变综合选项，如下图所示，再综合一次。
Keep Hierarchy：Yes
图 4-3. 综合属性
1. 在 Processes窗口中，右键点击Synthesize 选择Properties。
2. 在 Synthesis Options 中，设置 Keep Hierarchy为Yes，如图4-3。
注意：如果选择Keep Hierarchy（其实是指定了一个综合约束），实现工具在整个实现过程中保留设计的层次结构（指VHDL entities或者Verilog modules，而不是在综合过程中推译出来的macros）。
3. 点击 OK，并重新综合。
4. 打开Synthesis report ，在页面下面的Find中输入Timing Summary ，按Enter键找到报告中有关时序总结部分，回答下面问题。
③记录下估计的时钟频率，观察系统性能变化。
__________________________
5. 在页面下面的Find里输入Device Utilization ，点击Find Next，找到资源利用部分回答下面问题。
④在下表中记录资源利用情况：
Slices
Slice Flip Flops
4 input LUTs
IOBs
BRAMs
Global Clocks
DCMs
6. 在Find中输入Fanout，点击Find Next。
⑤哪一个NET有最大的fanout？它属于哪一个data path？
_______________________________
Fanouts 太大容易造成布线问题，通过对XST约束，可以限制fanout的数量。该限制并不需要特别考虑，特别是当它的数量小于30。
7. 右键点击Synthesize – XST 选择 Properties。
8. 在Xilinx Specific Options 选项中，输入Max Fanout数为50。点击 OK。(图4-4)
9. 双击 Synthesize – XST ，重新综合。
10. 打开 synthesis report ，查找 fanout，回答下面问题。
⑥哪条net的fanout 最大，它属于哪个data path？
___________________________
11. 在 synthesis report中，查找 timing summary，回答下面问题。
⑦设计的最大时钟频率是多少？
___________________________
图 4-4. Xilinx Specific Options
12. 在 Processes窗口中，展开 Implement Design ，双击 Place & Route 下面的Analyze Timing/FloorPlan Design (PlanAhead)。
13. 通过Tools → Show Hierarchy， 查看设计的层次结构（hierarchy）。（图4-5和图4-6）
图 4-5. 网表设计视图
图 4-6. 设计的层次视图
步骤4：下载和系统测试
步骤4产生FPGA配置比特流文件，并通过JTAG 下载线配置FPGA 。
1. 配置Falcon开发板上的configuration mode 选择跳线，选择配置模式为JTAG。
2. 连结下载线，给Falcon板上电。
3. 打开在实验3中创建的超级终端（波特率为9600）。
4. 双击 Generate Programming，生成比特流文件。
5. 展开 Configure target device ，双击manage configuration project（impact）
6. 当 impact对话框出现时，选择Boundary-Scan Mode ， 点击 Next，然后点击Finish。
7. 出现的提示框表明impact软件检测到两个器件，点击OK。
8. 分配 loopback.bit文件给xc3s250e 器件（JTAG 链中的第一个设备），为 platform flash PROM器件选择bypass。
9. 右键点击 xc3s250e 设备，选择 Program。
注意：下载成功后，在超级终端窗口中，你应当看到“Xilinx Rules”字样。
10. 拨动开关，在Falcon板上可以看到LED灯点亮。
结论
综合选项其实是对综合所施加的约束，不同的综合选项，综合出来的系统的性能不同。理解掌握综合提供的选项有助于提高系统设计性能。
答案
① 写下估计的时钟频率（用于与后来结果比较）。
Minimum period （verilog）: 11 ns （Maximum Frequency: ~107 MHz） Minimum period （VHDL）: ~8.15 ns （Maximum Frequency: ~122 MHz）
注意：实验结果与你使用的PC系统有关
② 写下资源占用情况：
Slices 163 （Verilog）/ 160 （VHDL）
Slice Flip Flops 147 （Verilog）/ 147 （VHDL）
4 input LUTs 303 （Verilog）/ 299 （VHDL）
IOBs 21 （Verilog and VHDL）
BRAMs 1 （Verilog and VHDL）
Global Clocks 2 （Verilog and VHDL）
DCMs 1 （Verilog and VHDL）
③ 记录下估计的时钟频率，观察系统性能变化
Minimum period （Verilog）: ~9.76 ns （Maximum Frequency: ~102 MHz）
Minimum period （VHDL）: ~8.68 ns （Maximum Frequency: ~115 MHz）
注意：实验结果与你使用的PC系统有关
④ 在下表中记录资源利用情况
Slices 167 （Verilog）/ 163 （VHDL）
Slice Flip Flops 147 （Verilog）/ 147 （VHDL）
4 input LUTs 303 （Verilog）/ 298 （VHDL）
IOBs 19 （Verilog and VHDL）
BRAMs 1 （Verilog and VHDL）
Global Clocks 2 （Verilog and VHDL）
DCMs 1 （Verilog and VHDL）
⑤ 哪条NET有最大的 fanout？它属于哪一个data path？
Verilog
LUT3:I2->O (operand_select_mux_1 (port_id<1>)) with fanout of 84
Data path: my_kcpsm3/reg_loop_register_bit_1 to transmit/buf_0/register_bit_3
VHDL
LUT3:I2->O (reg_loop.operand_select_mux (port_id<0>)) with fanout of 84
Data Path: my_kcpsm3/reg_loop.register_bit to transmit/buf/count_width_loop.register_bit
⑥ 哪条NET的fanout 最大，它属于哪个data path？
Verilog
LUT3:I2->O (operand_select_mux_1 (port_id<1>)) with fanout of 43
Data Path: my_kcpsm3/reg_loop_register_bit_1 to transmit/buf_0/register_bit_3
VHDL
LUT3:I2->O (reg_loop.operand_select_mux (port_id<0>) with fanout 43
Data Path: my_kcpsm3/reg_loop.register_bit to transmit/buf/count_width_loop.register_bit
⑦ 设计的最大时钟频率是多少？
Minimum period （Verilog）: ~11.7.ns （Maximum Frequency: ~85 MHz）
Minimum period （VHDL）: ~10.6 ns （Maximum Frequency: ~94 MHz）
注意：实验结果与你使用的PC系统有关
实验5： IP核生成器系统实验
目标板：Falcon-E25TG
介绍
实验5通过Xilinx CORE Generator™系统生成IP核，并嵌入到用户设计中。
目标
实验完成后，你将能够获得以下能力：
用Xilinx CORE Generator生成一个IP核
例化IP核到HDL设计中
对含有IP核的HDL设计进行行为仿真
通过开发板硬件验证设计
步骤
实验5使用CORE Generator生成器来生成PicoBlazer 的程序存储器，并例化到PicoBlaze应用系统中，最后在Falcon-E25TG开发板上完成硬件验证。
查看硬件设计，生成程序存储器ROM初始化文件
生成程序存储器IP核（BlockRAM）
例化程序存储器IP核到应用系统中
对应用系统行为仿真
在开发板上进行硬件验证
在实验手册的指导下，你将一步步地完成整个实验。如果你已经熟悉ISE软件设计流程，则可以跳过一步步的详细说明，自行完成实验。
注意： 符号引导的段落是对该段落下面各个步骤的说明，不是操作步骤。
讲义中需要用户进行操作的所有步骤均由小写阿拉伯数字引导。
步骤1：查看硬件设计，生成程序存储器ROM初始化文件
启动the ISE™ Project Navigator并打开工程文件
1. 选择开始 → 程序 → Xilinx ISE Design suite 12.4→ ISE Design Tools → Project Navigator，打开Xilinx ISE 12.4。
2. 点击 File → Open Project，选择coregen.xise ，点击 Open。
Verilog用户： 浏览D:\ ISE_Flows \ labs\ lab5\verilog\coregen
VHDL 用户： 浏览 D:\ ISE_Flows \ labs\ lab5\vhdl\coregen
浏览设计，可以看到有红色问号标记。使用以前实验的程序，完成Task #3，汇编生成尾缀为.coe的参数文件（coe用来初始化程序存储器ROM）。
3. 在D:\ ISE_Flows\Labs\lab5\vhd(Verilog)\Assembler目录中打开汇编应用程序program.psm 。
4. 编写程序代码，完成task #3，任务3通过超级终端显示从键盘输入的内容。
注意：编写代码时请参考代码中的注释。如果编写代码存在困难，请参考Solutions中相应内容。
5. 打开DOS命令提示符窗口，在命令提示符下输入下面命令：
> kcpsm3 program.psm
注意：汇编器将产生包括 .COE文件在内的几个文件。在使用Core Generator生成指令存储器ROM中，.COE文件用于对ROM数据初始化。
步骤 2：生成程序存储器IP核（BlockRAM）
创建一个类型为IP Core，名字为program 的新源文件。这个新源文件（IP Core）将使用BlockRAM。
1. 在Processes 窗口中，选择 Project→New Source。
2. 在New Source对话框中，选IP(CoreGen & Architecture Wizard)，并在File Name 空白处输入program。（图5-1）
图 5-1. New Source对话框
3. 点击 Next 。
4. 在 Select Core Type 对话框中, 展开Memories & Storage Elements，再展开RAMs & ROMs，选择Block Memory Generator v4.3。（图5-2）
图 5-2. 选择核类型对话框
5. 点击Next，点击Finish。
注意：1至2分钟时间后，CORE Generator™系统界面打开。
6. 如图5-3，按如下参数设置Dual Port Block Memory参数，点击Next。
元件名：program
存储内型：Dual Port ROM
内存大小：1024 x 18
图5-3. Block Memory 选项
7. 按图5-4设置Port A参数，并点击Next。
Read Width：18
Read Depth：1024
Operating Mode：Write First
Enable：Always Enabled
图 5-4. Port A 选项
8. 点击Load Init File ，选择刚才生成的Program.coe 文件 。（图5-5）
图 5-5. 用program初始化内存
注意：如果.coe文件格式不兼容（指定后文件是红色的），可使用文本编辑器修改.coe文件，只保留以memory_initialization 开头的文件行（2条），然后重新运行Load Init File步骤。
9. 点击Show按钮，从下拉框中选择memory_initialization_vector，可以观察程序存储器的初始化数据，如图5-6所示，然后点击OK。FPGA配置完成后，这些初始化数据将加载到作为程序存储器的BlockRAM中。
图 5-6. Block RAM 初始化内容
10. 点击next，点击finish。
注意：program.xco 文件应该已经被自动添加到当前工程中。
步骤3a：例化程序存储器IP核到应用系统中（Verilog）
注意：VHDL 用户不做此步，请直接跳到步骤 3b
例化在步骤2中产生的程序存储器ROM 核。
1. 在Sources 窗口中，双击 loopback.v， loopback.v 文件在右面窗口中被打开。
2. 在工程窗口的Hierarchy选中program，然后双击View HDL Instantiation Template （图5-7a）
图 5-7a. 例化模板
3. 复制并粘贴例化模板内容到 loopback.v 文件的注释语句“//Instantiate the ROM block here” 下面。
4. 按下面内容在loopback.v文件中编辑例化语句，完成信号连接：
program my_program (
.clka(clk55MHz),
.addra(address),
.douta(instruction),
.clkb(1'b0),
.addrb(10'b0000000000),
.doutb() );
5. 选择 File → Save。
步骤3b：例化程序存储器IP核到应用系统中（VHDL）
注意：Verilog 用户不做此步，请直接跳到步骤4
例化在步骤2中产生的程序存储器ROM 核。
1. 在Hierarchy 窗口中，双击 loopback.vhd，源文件在右面窗口中被打开。
2. 在工程窗口的Hierarchy选中program，然后双击View HDL Instantiation Template （图5-7b）
图 5-7b. Language Templates
3. 复制并粘贴例化模块中component declaration内容到 loopback.vhd 文件中。粘贴到loopback.vhd 文件中的注释语句--Insert component declaration for pro here后面。
4. 复制并粘贴例化模块中component instantiation内容到 loopback.vhd 文件中。粘贴到loopback.vhd 文件中的注释语句—Insert component instantiation for program here后面。
5. 按下面内容在loopback.vhd文件中编辑例化语句，完成信号连接：
my_program : program
port map (
clka => clk55MHz,
addra => address,
douta => instruction,
clkb => '0',
addrb => "0000000000",
doutb => open );
6. 选择File → Save保存。
步骤4：对应用系统行为仿真
检查 testbench 文件，理解发生了什么变化。
1. 在Hierarchy 窗口中，双击testbench.v/.vhd （如果没有，请参照前述步骤自行添加）。
查看testbench 的功能，注意以下注释部分：
The testbench toggles switches
Waits for some clock cycles
Checks the LEDs to see if they match the switch settings
2. 在Hierarchy窗口中，选择 program.xco。
3. 在Processes窗口中，展开CoreGen ，双击View Verilog/VHDL Functional Model。
注意：该文件来自XilinxCoreLib仿真实验模型库，在ISE内进行行为仿真时，将自动调用这个仿真模型。（对VHDL 用户，如果仿真模型文件没有出现，右键点击View Verilog/VHDL Functional Model，选择Open Without Updating）
运行行为仿真，仿真时间为 50000 ns。观察仿真波形，验证IP核已经正确嵌入。
4. 在Design窗口中，选择 Simulation ，选择 testbench.v/.vhd 。
5. 在Processes窗口中，展开ISim Simulator，双击 Simulate Behavioral Model 。
6. 在Simulation Run Time中输入50000ns。
7. 点击OK。
8. 双击Simulate Behavioral Model。
9. 观察仿真波形，分析LED灯端口信号的变化是否能够反映SWITCH端口信号的设置。
步骤5：在开发板上进行硬件验证
打开超级终端。 产生FPGA配置比特流文件，下载到实验板。
1. 按实验2中介绍新建一个超级终端，设置超级终端波特率为9600，连接好开发板，打开电源。
2. 在Processes窗口中，展开Configure Target Device，双击Manage Configuration Project (iMPACT)。
3. iMPACT窗口打开后，窗口中显示在JTAG链中检测到两个器件，点击OK 。
4. 为Spartan-3 xc3s25e器件分配loopback.bit文件，其余选择bypass。
5. 右键单击Spartan-3 xc3s250e ，选择program，点击OK，将通过JTAG下载线配置FPGA。
6. 下载成功后，在超级终端窗口将看到 “Xilinx Rules!“字样，在键盘上输入任意字符，观察超级终端窗口中的显示。
图 5-9. 在超级终端窗口观察输出
结论
实验5通过 CORE Generator™ system生成程序存储器IP核，并例化到设计中。VEO和 VHO 文件是例化模块，使用它们可以方便地完成IP 核的例化工作。.V 和.VHD 文件是仿真模块，用来支持IP核的行为仿真。
实验6：Chipscope调试实验
目标板：Falcon-E25TG
介绍
实验6通过将ILA/ICON 核嵌入设计中进行片上调试。
ChipScope Pro（在线逻辑分析仪）具有传统逻辑分析仪的功能，是针对Xilinx FPGA的在线片内信号分析工具。ChipScope Pro通过JTAG口，在线实时地读出FPGA的信号。
根据用户设定的触发条件，ChipScope Pro能够将用户关心的信号实时地保存到未使用的片内BlockRAM中，然后通过JTAG口传送到计算机上运行的分析工具，计算机屏幕上显示出时序波形。ChipScope Pro工具使FPGA不再是黑匣子，利用ChipScope Pro可以方便地观测FPGA内部的所有信号，对FPGA内部逻辑调试非常有利。
使用ChipScope Pro观察FPGA内部信号优点如下：
成本低廉：只要一根JTAG电缆和ChipScope Pro软件。
灵活性高：观察信号的数量和存储深度由器件剩余的BlockRAM数量决定，剩余Block-RAM越多，可观察信号的数量和存储深度就越大。
使用方便：ChipScope Pro能够读取设计网表（NGC、EDF或EDN文件），并自动将其自身（网表）插入到原设计网表中。用户可以方便地选择待观测信号，可以设置复杂的触发条件。ChipScope Pro只使用少量的查找表资源和寄存器资源，对原设计的影响很小。
目标
完成实验后，你将能够：
在ISE中创建Chipscope-Pro源文件。
使用Chipscope-Pro 创建 ILA核和 ICON 核，并例化到设计中。
使用Chipscope Analyzer设置触发选项。
在Chipscope Analyzer中下载FPGA配置比特流文件。
运行片上调试功能，在Chipscope Analyzer 中观察波形。
步骤：
实验6中修改PicoBlaze 软件应用程序，使用Chipscope-Pro 运行片上调试功能。
实验主要由4步组成：
添加Chipscope工程文件到当前设计
修改ILA参数，并连接信号
配置Chipscope Analyzer软件，更新设计
运行片上调试功能 。
在实验手册的指导下，你将一步步地完成整个实验。如果你已经熟悉ISE软件设计流程，则可以跳过一步步的详细说明，自行完成实验。
注意： 符号引导的段落是对该段落下面各个步骤的说明，不是操作步骤。
讲义中需要用户进行操作的所有步骤均由小写阿拉伯数字引导。
设计概要：
实验6使用Chipscope-Pro 插入ICON 核和 ILA核到当前设计中，ILA核的触发端口是设计中uart_rx 和 uart_tx模块信号的反馈。接下来，通过超级终端文本输入，你可以设置触发器捕获数据。当缓冲满了，你应该在Chipscope上看到结果。
步骤1：添加Chipscope工程文件到当前设计
打开 ISE™ Project Navigator并打开工程文件。
1. 选择开始 → 程序 → Xilinx ISE Design suite 12.4→ ISE Design Tools → Project Navigator，打开 Xilinx ISE 。
2. 选择 File → Open Project
Verilog 用户：浏览到D:\ISE_Flows\ labs\lab6\ verilog\chipscope
VHDL 用户:：浏览到D:\ISE_Flows \labs\lab6\ vhdl\chipscope
3. 选择 chipscope.xise点击 Open。
通过 Project Navigator创建 Chipscope-Pro 工程。
4. 选择 Project New Source ，打开建立新源文件对话框，点击 Chipscope Definition and Connection File，输入文件名loopback_cs。点击Next。（图6-1）
图 6-1. 新源文件对话框
5. 在Sources 窗口中，选择 loopback 文件做为 source文件，点击next， 然后点击 finish。Chipscope-Pro 源文件将添加到工程窗口的Sources中。（图6-2）
图 6-2. 添加Chipscope Definition and Connection (.cdc)
步骤2：修改ILA Core参数，并连接信号
插入 ICON 和ILA核到当前设计网表中。连接累加器的输出到触发器和ILA核的输入端。
1. 双击loopback_cs.cdc文件，打开Chipscope-Pro工程（ Inserter界面）。（图6-3 ）
图 6-3. Chipscope-Pro Core Inserter
注意： Chipscope-Pro工程保存相关的源文件、目标文件、核参数和核设置。
2. 点击next，点击右下角的New ILA Unit按钮，或者选择Edit菜单下的New ILA Uni命令。注意左上角窗口里出现U0:ILA。（图6-4）
图 6-4. 嵌入新的 integrated logic analyzer (ILA) 单元
3. 点击 next，开始设置触发参数。
每一个ILA 或者ILA/ATC核都有16个独立的触发端口，可以分别进行设置。触发端口是总线结构，该总线结构由独立的信号或者范围从1到256的bit位组成。每一个触发端口可以连接1到16个匹配单元。
每个匹配单元其实就是一个比较器，分别连接到一个触发端口，用于检测触发端口的事件。一个或多个匹配单元组合起来，构成完整的触发条件事件，该事件用来控制数据捕获。ILA和ILA/ITC核支持6种不同类型的匹配单元，不同的匹配单元执行不同的比较功能通。
在实验6通过某些UART控制信号来设置 ILA 核。
4. 按下面数据设置ILA触发参数后，点击next。（图6-5）
触发输入和匹配单元设置：
Number of input trigger ports：3
Trigger Port Trigger Width # Match Units Counter Width Match Type
TRIG0 1 1 Disabled basic
TRIG1 1 1 Disabled basic
TRIG2 1 1 Disabled basic
Trigger Condition设置：
Enable Trigger Sequencer：选中（用于指定使能触发事件的顺序）
Max Number of Sequencer Levels：2
Storage Qualification Condition设置：
Enable Storage Qualification：选中 (用于指定存储哪些数据 )
图 6-5. 指定触发参数
ILA核能够存储在采样缓冲区的采样数据的最大值叫存储深度（data depth） 。存储深度和数据宽度（data width）相互制约，取决于设计中剩余的blockRAM 的大小。
5. 设置下面的选项，点击next。（图6-6）
Data Depth：512
Sample On：Rising clock edge
Data Same as Trigger Port：unchecked
Data Width：8
图6-6. Specify Trigger Parameters
Net Connections 把ILA或者 ILA/ATC 核与所选择的信号连接起来。用户需要分别指定时钟、触发和数据连接。没有连接将显示红色。（图6-7）
图6-7. Unconnected Net Connections
6. 点击 Modify Connections 按钮，出现Select Net界面。（图6-8）
图6-8. Net Connections
Select Net对话框提供一个简单的图形化界面将选择的观察信号与ILA或者ILA/ATC核连接起来。通过使用左上窗口的Structure/Nets，可以浏览当前设计的层次结构，从而方便地选择欲观察的信号。
7. 选择在Net Selections下的Clock Signals 选项卡，在左边网络列表中点击 cl 信号 ，然后点击右下角的 Make Connections 按钮 ，将把clk55MHz 信号连接到ILA核的时钟端口。（图6-9）
图 6-9. 连接时钟信号
8. 点击Trigger Signals选项卡，连接三个触发端口。（图6-10）
TP0：data_present （该信号指示数据出现在uart_rx 模块）
TP1：read_from_uart （这是uart_rx模块的输入信号，表示读操作将发生）
TP2：write_to_uart（这是uart_tx模块的输入信号，表明写操作将发生)
图6-10. 连接触发端口
9. 点击 Data Signals选项卡，将PicoBlaze数据输出端口out_port与ILA核数据端口连接起来，如图6-11所示，然后点击OK。
图 6-11. 连接PicoBlaze 输出端口
10. 注意到 Net Connections 窗口下的Clock端口、Trigger端口和Data端口均显示黑色，表明所有连接有效。点击Return to Project Navigator，保存文件。（图6-12）
图 6-12. 连接 Design与ILA 核
步骤3：配置Chipscope Analyzer软件，更新设计
Chipscope-Pro Analyzer 工具通过ICON核连接到ILA核。可以通过Chipscope-Pro Analyzer配置FPGA，选择触发条件，设置控制台，观察捕获数据等。可以有多种方式处理捕获的数据。
1. 在Hiersrchy 窗口中，点击顶层文件 loopback.v/vhd ，双击Processes 窗口中的Analyze Design Using Chipscope ，打开Chipscope Analyzer工具。
2. 连接Falcon-E25TG板下载线，打开板上电源。
3. 点击Chipscope Analyzer窗口左上角的Open Cable/Search JTAG Chain 按钮 。（图6-13）
图 6-13. 建立JTAG连接
4. 在JTAG chain中可以找到2个器件，分别是Spartan-3E xc3s250e和Platform Flash xcf02s或者xcf04s，点击OK。
5. 右键点击 xc3s250e ，选择configure。
6. 点击 Select New File，浏览到当前工程目录，选择 loopback.bit，注意到.cdc文件也同时被添加到工程中，点击OK。
Chipscope Pro Analyzer 界面由四部分组成。
每一个 Chipscope Pro ILA、ILA/ATC 和IBA核都有自己的触发设置窗口，该窗口提供图形化界面设置触发器。每个Chipscope Pro核的触发结构可以实时修改，不需要重新综合实现。触发结构有三个要素：
Match Functions：定义每个匹配单元的比较值。
Trigger Conditions：基于二进制等式或者一个/多个匹配功能序列，定义完整触发条件。
Capture Settings：定义采样数据数量，采样窗口数量和触发器在采样窗中的位置。
实验6将在PicoBlaze输出端设置触发器，捕获其发出的文本数据。
图6-14. Chipscope Analyzer 窗口
7. 指定下面的 Match Units 。（图6-15）
Radix：二进制
M0:TriggerPort0（data_present）：Value 1
M1:TriggerPort1（read_from_uart）：Value 1
M1:TriggerPort1（write_to_uart）：Value 1
图6-15. 设置匹配单元
8. 点击Trigger Condition Equation 下的区域，选择Sequencer选项卡下面的选项，产生M0 → M1表达式，然后点击OK。
图6-16. Trigger Condition Equation
9. 点击Storage Qualification附近的区域, 选择 AND Equation，点击M2，点击OK。这样，当write_to_uart信号变成高电平时，将使能捕获数据存储。
图 6-17. Storage Qualification Equation
步骤4：运行片上调试功能
步骤4导入一个.cdc文件。运行片上调试功能，观察调试结果。
1. 执行下面操作，生成由8位out_port 信号构成的总线。
选择信号，从out_port<0> 到out_port<7>。
右键点击这些信号，选择Add to Bus New Bus ，创建总线output_port。
图 6-18. 创建一个新的output_port 总线
2. 设置数据缓存器深度（depth）： 16。（图6-19）
图 6-19 选择数据缓存器深度
3. 点击Apply Settings and Arm Trigger 按钮。（图6-20）
图 6-20. Apply Settings and Arm Trigger
4. 在超级终端输入“Xilinx #1 FPGA!” ，在Chipscope Analyzer中观察信息。右击out_portBus Radix，选择ASCII格式。（图6-21）
图 6-21. 验证捕获结果
结论
嵌入ILA 核和 ICON 核到 PicoBlaze应用设计中，在Chipscope Analyzer中设置触发条件，运行片上调试功能，在Chipscope-Pro Analyzer中分析波形。
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FALCON-E25TG FPGA development Platform ISE Process experiment manual
Version 3.1, November 2011
FALCON-E25TG Type FPGA development platform
Ise Process Experiment Manual
Experimental 1:xilinx Ise tool flow Experiment P02-P14
Experimental 2:architecture Wizard and pin distribution experiment P15-P27
Experiment 3: Global timing constraint Experiment P28-P40
Experiment 4: Comprehensive technical Experiment p41-p49
Experimental 5:IP Nuclear generator system experiment p50-p57
Experimental 6:chipscope Debugging Experiment p58-p69
Experimental 1:xilinx ISE tool flow Experiment
Target board: Falcon-E25TG
Introduced
Describes the basic usage flow of the ise™ tool through the sample program.
This experiment is suitable for users to understand and verify the knowledge after learning the design process of ISE tool and the principle of Picoblaze microcontroller.
Goal
After completing the sample experiment, you will have the following capabilities:
Create a new project
familiar with FPGA design basic process
Master the basic technical features of Picoblaze
Lab Preparation
1. Copy the Labs-materials/ise-flows folder on the disc to the D: root directory. Or unzip the Ise_flows.rar directly under the CD Labs-materials directory to the D: root directory.
2. Connect the JTAG interface of the computer with the port and the FALCON-E25TG experimental board by downloading the cable.
3. Connect one end of the RS232 serial line to the computer, and the other end is connected to the RS232 port of FALCON-E25TG.
Note: In each of the following experiments, follow this preparation.
Steps
Experiment 1 is done mainly through the following four steps:
Create a new project
Add source program files for the project
Design Simulation (Simulation)
Design Implementation (Implementation)
Under the guidance of the Experimental Manual, you will complete the whole experiment step by step.
If you are already familiar with the ISE software design process, you can skip the detailed instructions in one step and complete the experiment yourself.
Note: The symbol-guided paragraph is a description of the following steps in the paragraph, not an action step.
All steps in the handout that require the user to operate are guided by lowercase Arabic numerals.
Step 1: Start
View the 8-bit microcontroller Picoblaze document and familiarize yourself with its structure and instruction set. This experiment uses Picoblaze interrupt application as ISE design process use case, it is necessary to learn picoblaze structure and instruction set, but not necessary.
Picoblaze user manual kcpsm3_manual.pdf stored in D:\ Ise-flows \ labs \ LAB1 \ Verilog (or vhdl) \ KCPSM3 \ docs\ directory.
Open ISE Project Navigator to create a new project.
1. Select "Start → program →xilinx ise design suite 12.4→ise Design Tools→project Navigator" (or double-click the desktop Xilinx ISE Design Suite 12.4 icon directly ), start Ise Project Navigator.
2. In the Project Navigator interface, select the File→new Project menu or choose directly to do the upper part of the icon and open the new project Wizard (Figure 1-1).
3. Through "..." button to browse the following directory, and then click on the list.
Verilog User: D:\ Ise-flows \ labs \ LAB1 \ Verilog
VHDL User: D:\ ise-flows \ labs\ lab1 \ VHDL
Figure 1-1. Create a new Project wizard
4. Under Name, enter Flow_lab.
5. Click Next.
6. The Device Properties dialog box appears (Figure 1-2).
Figure 1-2. Device Properties dialog box
7. After selecting the options below, click Next:
device family:spartan3e
device:xc3s250e
package:tq144
speed Grade:–4
synthesis tool:xst (Vhdl/verilog)
simulator:ise Simulator (Vhdl/verilog)
preferred Language:verilog or VHDL (select the language you use)
8. The dialog box appears as shown in the following illustration, click Finish (Figure 1-3).
Figure 1-3. Project Summary dialog box
Add HDL source files to the project.
9. Click Project–add Copy of Source or click on the right toolbar to browse to D:\ Ise-flows \ labs \ LAB1 \ VHDL (or Verilog) \ KCPSM3 \vhdl (or Verilog) folders.
10. Select the Kcpsm3_int_test and kcpsm3 files under the VHDL or Verilog folder and click Open.
11. Click Next and click Finish. The following dialog box (Figure 1-4) appears, indicating that you have chosen correctly.
12. Click OK to accept the default settings.
Figure 1-4. Adding Source Files dialog box
Figure 1-5. Sources Window in Project Navigator
Note: There is a small red question mark in front of the Program-int_test module in Figure 1-5. This is because the top-level file kcpsm3_int_test.vhd/v contains an illustrated statement of the int_test.vhd/v module that has not yet been added to the current project. The int_test.vhd/v module is used to generate a picoblaze command memory ROM (using 1 Blockram-generated ROM). Step 2 discusses the generation of the instruction memory ROM.
Step 2: Generate instruction Memory
In this experiment, Picoblaze's assembly application has been written and stored in the INT_TEST.PSM file (Note: Learning this program contributes to the understanding of the experiment). Compiling this file using the Picoblaze's own assembler will result in a int_test.vhd file, a int_test.v file, and an instruction memory output file such as Int_test.coe. Depending on the language used in the selection of one of the first two files into the current design top-level file (kcpsm3_int_test), the integrated tool can automatically push (infer) out of the picoblaze instruction memory (Rom generated by 1 blockram). In addition, using the third file Int_test.coe, the picoblaze instruction memory can also be illustrated by the Coregenerator tool.
1. Open Windows Browser and browse to D:\ Ise-flows \ labs \ LAB1 \ VHDL (or Verilog) \ KCPSM3 \ Assembler folders.
Note: KCPSM3.exe assembly tools, 3 Rom_form template files, and two. PSM assembly source files are all in this directory (Figure 1-6). When the compilation is complete, all output files also appear in this directory.
Figure 1-6. Compiling catalog Content
2. Open the INT_TEST.PSM file using a text editor. Refer to (ug129) Picoblaze 8-bit Embedded microcontroller User Guide and KCPSM3 manual to understand the source program. (These reference documents are in D:\ Ise-flows \ labs \ LAB1 \ VHDL (or Verilog) \ KCPSM3 \ Documents subdirectory)
3. Open the DOS command window. ("Start program xilinx design Suite 12.4accessoriescommand Prompt")
4. Use the CD command to browse to the assembler directory (Figure 1-7).
D:\ Ise-flows \ labs \ LAB1 \ Vhdl\KCPSM3\Assembler
or d:\ Ise-flows \ labs \ LAB1 \ Verilog\KCPSM3\Assembler
Figure 1-7. Command Window
5. Enter the assembly code below the command prompt (Figure 1-7), which will automatically produce the instruction memory output file.
KCPSM3 INT_TEST.PSM
Note: init_test.vhd (VHDL language program for generating instruction Memory), INT_TEST.V (Verilog language program for generating instruction memory) and Init_ can be seen in the current directory. Test.coe (an initialization data file for the Coregenerator tool to generate instruction memory). In fact, all three files are stored in the machine code generated after the application is compiled, and the user can open the three files and view the binary machine code portion of the system.
6. In ISE Project Navigator, Projectadd Copy of Source found in directory path D: \ ise-flows \ labs \ lab1 \ vhdl \KCPSM3 \ Assembler Int_test.vhd or INT_TEST.V file. (Fig. 1-8)
Figure 1-8. Add a int_test.vhd file to the current project
7. Click Open and click OK. In this way, we add the Init_test.vhd or INIT_TEST.V file to the current project. (Fig. 1-9)
Figure 1-9. Hierarchical view of Picoblaze design
Note: The top-level file kcpsm3_int_test.vhd/v contains an example statement of the int_test.vhd/v module. Therefore, after adding the source code int_test.vhd/v to the current project, the small red question mark in front of the program module disappears, that is, the program module is no longer an "empty box" in the current project. (Figure 1-9)
Step 3: Behavior simulation
In step 3, the user adds TESTBENCH.VHD/.V code to the current project, uses the Xilinx ISIM emulator to complete the behavior simulation (behavioral simulation), and examines the simulation results. The TESTBENCH.VHD/.V code is a simulation test bench file, which describes the generation of input excitation for the test module and the processing of the output results, which cannot be used for comprehensive implementation. In this experiment, the TESTBENCH.VHD/.V file has been written and can be used directly. In the user's own design, you need to write this file yourself.
1. In Ise Project Navigator, click Projectadd Copy of Source, point to D:\ Ise-flows \ labs \ LAB1 \ VHDL (or Verilog) \ KCPSM3 \ vhdl (or Verilog) directories.
2. Select the Test_bench.vhd or TESTBENCH.V file and click Open.
Figure 1-10. Select Test_bench.vhd (or testbench.v) file
3. As shown in Figure 1-10, click OK and the test bench.vhd file is added to the current project.
4. As shown in Figure 1-11, select Set to simulation in the view window.
Figure 1-11. Sources Window containing test bench
5. As shown in Figure 1-12, click test_bench.vhd/v in the Sourcese window to display the Xilinx ISE Simulator toolbar in the Processes window. Click the plus sign in front of the toolbar, right-click the simulator behavioral Model, select Properties, and open the Properties dialog box. As shown in Figure 1-13, enter 10000ns at simulation run time, click the OK button, and close the Properties dialog box.
Figure 1-12. Show Xilinx ISE Simulator toolbar in Processes window
Figure 1-13. Setting simulation Properties
6. Double-click the simulate behavioral Model to simulate the behavior of the design. Click the window to enlarge the icon, select the name bar in the waveform window, right-click Radix-hexadecimal, you will see three interrupt pulses and their interrupt values, the simulation results waveform shown in the following figure (Figure 1-14).
Figure 1-14. Isim Behavior Simulation Results
7. Use the magnification tool in the toolbar to enlarge the simulation results graph to confirm that the simulation results are correct.
Note: in D: \ ise-flows \ labs\ lab1 \ vhdl \ KCPSM3 \ Assembler directory, the file Int_test.log records the address and machine code of each instruction in the instruction memory, and the user can verify the correctness of the simulation results against this file. 。
8. Close the simulation window to end the simulation.
Step 4: Implementation of the design
Step 4 implements the design.
1. As shown in Figure 1-15, in the Sources window of the project, select implementation and click the top-level file kcpsm3_int_test.vhd/v of the project.
Figure 1-15. Sources window
2. As shown in Figure 1-16, in the Processes window, double-click Implement Design.
Figure 1-16. Processes for source window
3. Expand the plus sign before implement DESIG and you will see three steps to implement it. After each step runs, a small icon appears before the step to indicate the completion of the step. The icon indicates as follows:
Indicates that the procedure completed successfully
Indicates that the procedure is complete but has a warning message
Indicates that the action step was not completed due to an error
Note: During the implementation process, the message window at the bottom of Project Navigator displays the various messages generated by the implementation process in real time.
4. When each action step is complete, a corresponding report is generated that contains the details that are generated during the step run. These reports can be accessed directly in the detailed reports section of the Design Summary window in the Ise Project Navigator, or by clicking the appropriate command under the steps in the Processes window. As shown in Figures 1-17, 1-18, 1-19.
Figure 1-17. Design Summary Window General Information
Figure 1-18. Resource utilization information in the Design Summary window
Figure 1-19. Access various reports in the detailed reports section of the Design Summary window
Conclusion
In Experiment 1, we completed the main steps of the ISE design: Creating a project, adding source files, simulation design, and design implementations.
In Experiment 2, we will learn to review various design reports, analyze designs, and check whether the area and performance metrics of the design meet the requirements.
Experimental 2:architecture Wizard and pin distribution experiment
Target board: Falcon-E25TG
Introduced
This paper introduces the PIN allocation tool of Structure Wizard and Planahead and its application.
Goal
After completing this experiment, you will be able to:
1. Configure a DCM component using the Structure Wizard
2. Example of DCM components into the design
3. Assign pin position using Planahead
4. Perform design confirmation pin allocation
5. Download to hardware for testing
Design Overview
Experiment 2 uses the UART real-time clock (real-time clock) module to complete a band on the FALCON-E25TG board that can view and set the time via HyperTerminal? Heart seed any neon stool pen our unitary low field art real-time clock module and its use documents can be found in the free Picoblaze distribution package.
This system is designed to achieve real-time clocks with hours, minutes and seconds, and has the ability to set alarm clocks. The system uses HyperTerminal software to set up, view time information and alarm clock information through UART serial message.
Some simple ASCII commands will be used in the experiment. When the "KCPSM3>" prompt appears in the HyperTerminal window, you can send action commands to the Development Board system via the keyboard. The wrong action command will have a "syntax error" message on the HyperTerminal, and the "Invalid Time" message will appear at the wrong time setting. If the command transfer is faster than the design processing (such as accepting the cache to fill), the "Overflow error" message will appear (which is unlikely to happen, of course).
The system requires a working clock of $ MHz. Because the FALCON-E25TG board only provides a clock of $ MHz, you need to use the Structure Wizard (architecture Wizard) to sample the DCM module and output the $ MHz working clock.
Steps
This example consists mainly of four parts:
1. Configure DCM using the Structure wizard;
2. Example of DCM to vhdl/verilog design;
3. Assign pin position;
4. Implement the design, download the design, verify the design through the Development Board.
Under the guidance of the Experimental Manual, you will complete the whole experiment step by step.
If you are already familiar with the ISE software design process, you can skip the detailed instructions in one step and complete the experiment yourself.
Note: The symbol-guided paragraph is a description of the following steps in the paragraph, not an action step.
All steps in the handout that require the user to operate are guided by lowercase Arabic numerals.
Step 1: Configure DCM using the Structure Wizard Architecture Wizard
Open the existing project.
1. Select start → All Programs →xilinx ise design Suite12.4→ISE design Tools→project Navigator, into the ISE Project Navigator environment;
2. Select File→open Project and point to the following directory to select Arwz_pace.xise to open the project;
Verilog users:d:\ise_flows\ labs\ Lab2\verilog\arwz_pace
VHDL users:d:\ise_flows\ labs\ Lab2\vhdl\arwz_pace
The design does not yet have an example of the DCM module. The following steps use the Structure Wizard to configure a DCM with an input clock of 50MHz and an output clock of 55MHz.
1. Select Projectnew Source.
2. In the source window that opens, select IP (Coregen architecture Wizard) and enter MY_DCM as the file name.
Figure 2-1 Selecting IP (Coregen architecture Wizard)
3. Click Next.
4. Expand FPGA Features and designclockingspartan-3e in the Select IP Type window, Spartan-3A, and select single DCM SP v12.1i. (Fig. 2-2)
Figure 2-2. Architecture Wizard Selection Box
5. Click Next and click Finish.
6. In the Xilinx clocking wizard–general Setup window, set the following options (Figure 2-3):
clk0, CLKFX and LOCKED: choosing
rst Box: Not selected
input lock Frequency: Fill in $ MHz
Figure 2-3 Xilinx clocking wizard–general Setup window
Note: The input frequency is indicated in clocking Wizard, and the Structure Wizard automatically configures DCM's operating mode (high frequency mode or low frequency mode). Based on the input clock frequency, the Structure wizard can calculate whether the required output frequency is within the allowed range. In addition, if the CLKFX output is selected, the Structure Wizard calculates the output frequency size of the CLKFX and estimates the clock jitter.
7. Click Next.
8. In the Xilinx clocking Wizard–clock buffers window (Figure 2-4), select the default value and click Next.
Figure 2-4 Xilinx clocking wizard–clock buffers window
9. Fill in 55MHz under the "Output Frequency of the Xilinx clocking wizard–clocking Frequency Synthesizer dialog box. (Fig. 2-5)
Figure 2-5 Specifying DCM output frequency
10. Click the Finish button to see My_dcm.xaw added to the current project in the Sources window of the project, but not to the file hierarchy of the top-level design module, which requires the next example (Figure 2-6).
Note: If you do not see My_dcm.xaw in the Sources window of the current project at this time, you can add it manually through Projectadd source. (Fig. 2-6)
Figure 2-6 lists DCM in the design hierarchy
Step 2a: Example of DCM to Verilog design
Note: VHDL users skip this step,? Benzene hard Comfort Street? b
All necessary files required for the current project have been created, and step 2a will be an example of the DCM module in the top-level design. Experiment 2 completes the example by copying the relevant content in the sample template and then pasting it in the top-level design.
1. In the Sources window, double-click uart_clock.v to open the source code.
2. In the Sources window, select My_dcm.xaw. Double-click View HDL instantiation Template in the Processes window, and the sample template for the MY_DCM module opens in the editor on the right. In the example template (file Form My_dcm.tfi), copy the Component Declaration section (under the//instantiate the module annotation) and paste it under the UART_CLOCK.V Insert DCM//here note in component code;
3. The MY_DCM port connection signal in the experiment does not use the system default name, need to modify the MY_DCM port connection signal, the specific modification please refer to the following code (you can also copy and paste the following code into the UART_CLOCK.V code//Insert DCM Below the component here Note).
MY_DCM INST_MY_DCM (
Clkin_in (CLK),
Clkfx_out (Clk55MHz),
Clkin_ibufg_out (),
CLK0_OUT (),
Locked_out (lock));
4. Define DCM's 55MHz output connection signal under annotation//signals for DCM:
Wire clk55MHz;
Note: At this point, the UART_CLOCK.V design has been updated and all clock signals have been renamed to the new Clock (clk55MHz).
5. Add the lock output port to the top-level entity:
Module Uart_clock (TX, RX, Alarm, CLK, Lock)
Output TX;
Input rx;
Output alarm;
Input CLK;
Output lock;
Note: The lock output port will drive the LD0 light of the FALCON-E25TG board. When hardware is debugged, the LD0 light indicates that DCM has successfully implemented the clock lock.
6. Click File→save to save the file. At this point, the module My_dcm.xaw is plugged into the correct location at the top-level design module file hierarchy. (Fig. 2-7)
Step 2 B: Example of DCM to VHDL design
Note: Verilog users skip this step!
All necessary files required for the current project have been created, and step 2b will be an example of the DCM module in the top-level design. Experiment 2 completes the example by copying the relevant content in the sample template and then pasting it in the top-level design.
1. In the Sources Project window, double-click Uart_clock.vhd to open the source code.
2. In the Sources window of the project, select My_dcm.xaw, double-click View HDL instantiation Template in the Processes window, and the sample template file (My_dcm.vhi) is opened. In the HDL-only template file, copy the component declaration (from component MY_DCM to end component) and paste it into the UART_CLOCK.VHD code annotation statement-Insert DCM Component Declaration below here;
3. Modify the port connection signal according to the following code, or copy and paste the following code into the annotation statement in UART_CLOCK.VHD code-Insert DCM component instantiation below).
Inst_my_dcm:my_dcm
PORT MAP (
Clkin_in => CLK,
Clkfx_out => Clk55MHz,
Clkin_ibufg_out => Open,
CLK0_OUT => Open,
Locked_out=> lock);
4. Under the annotation statement--signals for DCM, define the DCM output connection signal for DCM:
Signal clk55mhz:std_logic;
Note: The UART_CLOCK.VHD design has been updated. All clock signals have been renamed to the new Clock (clk55MHz).
5. Add the lock output port to the top-level entity:
Entity Uart_clock is
Port (
Tx:out std_logic;
Rx:in std_logic;
Alarm:out std_logic;
Clk:in std_logic;
Lock:out std_logic);
End Uart_clock;
Note: The lock output port will drive the LD0 light of the FALCON-E25TG board. When hardware is debugged, the LD0 light indicates that DCM has successfully implemented the clock lock.
6. Click File→save to save the file. At this point, the module My_dcm.xaw is plugged into the correct location at the top-level design module file hierarchy. (Fig. 2-7)
Figure 2-7. Hierarchical diagram of design files after routine completion
Step 3: Assign pin position
Steps 1 and 2 complete the design of adding DCM modules. The input and output ports of the FPGA need to be assigned to the pin position before the design implementation is carried out. In this step you will use the Planahead tool for pin allocation.
1. In the hierarchy window of the project, select the top-level design file UART_CLOCK.VHD/.V.
2. In the Processes window of the project, expand User Constraints and double-click Io-pin Planning (planahead)-pre-synthesis to open planahead.
Note: When asked if you have added a UCF file to the project, click "Yes".
3. If the Introduction window appears, click Close to turn it off.
Note: For VHDL users, 8 errors may be reported, ignoring them because they are not produced by design.
4. Select the CLK signal in the I/O Ports window, type p54 in the position box in the I/O Ports Properties window, and then click Apply. Select the Configure option, and then select LVCMOS33 as the interface standard. Other numbers are performed in a similar way (refer to the Lab2_ucf.txt file under D:\ISE_FLOWS \ UCF folder, and the FPGA pin position corresponding to the I/O port appears after "LOC ="). As shown in Figure 2-8 (Configure the constraint view of the pins).
CLK: 50MHz Crystal Vibration connected to the Development Board
lock: Connect the LD0 lamp on the Development Board
alarm: Connect the LD1 lamp on the Development Board
RX: Serial data receiving PIN for MAX3232 chip connected to the Development Board
TX: Serial data sending pins connected to the MAX3232 chip on the Development Board
Figure 2-8: Pin constraint view
5. Select a pin (such as CLK) in the I/O ports window and click the Fit Selection button to display the device and encapsulated view of the selected Pin, as shown in Figure 2-9.
6. Click File-save Design to save the pin assignment.
7. Click File-exit Exit Planhead and click OK.
Figure 2-9. Device and Package view
8. Click the Uart_clock file in the Sources window, expand user Constraints in the Processes window, double-click Edit Constraints (Text), and observe through Planahead in Uart_ The constraint file generated in CLOCK.UCF. Observe the text content of the UCF file and confirm that the PIN assignment is correctly written to the constraint file. It was observed that there was an error in the path name of the UCF file, as shown in Figures 2.10 and 2.11.
Figure 2.10 Before modification
Figure 2.11 After modification
Step 4: View the run report and set up HyperTerminal
Implement the design, view the report report, and confirm that the PIN allocation meets the requirements. Set up HyperTerminal.
1. In the Sources window of the current project, select the top-level design file UART_CLOCK.VHD/.V.
2. In the processes window of the current project, expand implement Design, and then expand the place in the Back-annotate Route to expand the Pin locations.
3. Double-click the View Locked Pin Constraints (Project Navigator automatically decides which programs need to run and the report is turned on when they are finished running).
4. Review the run report to see if the pin allocation completed in step 3 is implemented correctly.
5. Open HyperTerminal. The steps are: Start program attachments communication HyperTerminal.
6. Take a name for HyperTerminal and click OK. Specifies that COM1 is a port connection.
7. Set the following parameters for the port. Then click OK to complete the settings (Figure 2-12).
digits per second: 38400
Data bits: 8
Parity: None
Stop bit: 1
Data flow control: None
Figure 2-12. Serial Port Communication settings
8. Select the File menu in the HyperTerminal window, click the Properties button, select Settings, click ASCII code settings, select the check box to attach the line break to the end of the incoming line (Figure 2-13). Click Confirm to complete the property settings.
Figure 2-13. ASCII settings for serial port connections
Step 5: Download the design
Generate a download bitstream (bitstream) file and download it to the FPGA.
1. Connect the power adapter, Jtag download line and serial communication cable for the FALCON-E25TG Development Board, and turn on the FALCON-E25TG Development Board power switch.
2. Select the top-level file UART_CLOCK.VHD/.V, double-click Generate programming file, and produce a bitstream file that can be downloaded to the FPGA.
3. When the bitstream file is generated, expand generate programming file and double-click Manage Configuration Project (impact).
4. Click the Initialize Chain button, point Yes, browse to the project catalog selection Uart_clock.bit
Figure 2-14. JTAG chain with configurable files assigned
5. In the impact window, right-click xc3s250e, select Program, and click OK in the Programming Options dialog box. Configure the Bitstream file to start downloading to the FPGA if the download successfully appears in program Succeeded.
Note: After the download is successful, a kcpsm3> prompt appears in the HyperTerminal. (If the kcpsm3> prompt does not appear, move the cursor inside the HyperTerminal and press the BACKSPACE key)
Figure 2-15. Super Terminal display window
Step 6: Run the Urat real-time clock
Commands are issued to the system through HyperTerminal to verify the correctness of the design. You can refer to the manual for detailed instructions. (Manual for Uart_real_time_clock.pdf)
1. After entering the "time" command after the kcpsm3> prompt, enter the current clock in HH:MM:SS format in the HyperTerminal (Figure 2-16);
Figure 2-16. Display the current time
2. When you enter the "alarm" command after the command prompt, the current set alarm (alarm) time is displayed in hh:mm:ss form. Note that the alarm feature is turned off at this point (Figure 2-17).
Figure 2-17. Display alarm time and status
3. Enter the "alarm on" command after the command prompt and the alarm (alarm) function is turned on.
4. After entering "alarm 00:00:30" after the command prompt to set the alarm time 30 seconds, enter "Time 00:00:00" set the current time, 30 seconds later, the LD1 light on the board lit.
5. Enter the "alarm off" command after the command prompt and the LD1 light goes off.
Conclusion
In this experiment, you use the Structure Wizard Architecture Wizard to configure the DCM module and sample it into the current design. Use Planahead to assign the pin position of the IO port. Finally, implement and download the design and complete the verification in the hardware.
Experiment 3: Global timing constraint experiment
Target board: Falcon-E25TG
Introduced
Experiment 3 learns to use global timing constraints to improve the working clock frequency of the design.
Experiment 3 learns to analyze design performance using Post-map static Timing the Post-place and Post-place&route static Timing.
Goal
After completing the experiment, you will be able to:
Enter global timing constraints using Xilinx Constraints Editor
Observe the reasonable index of timing constraint of Post-map Static Timing
For each timing constraint, use the Post-place and Route Static Timing to view the critical path
Design Overview
In the Xilinx development environment, the constraints of implementing the pre-input are called logical constraints, and logical constraints are saved in the UCF file. Users can create and edit UCF constraint files directly, but they need to be familiar with the syntax of UCF files and the naming of components such as triggers, networks, and PD in the design, while using the constraint editor (Constraints Editor) to create and modify constraints can reduce requirements and increase efficiency.
Experiment 3 hardware design principle as shown in Figure 3-1, is a picoblaze system with UART peripherals.
Figure 3-1. Picoblaze system
The main task of this experiment is to implement a loop test (loopback test) system with Picoblaze assembly language programming. The Loop test system first sends a signal to a device, and then returns a signal from the device to test that the device is working properly.
As shown in Figure 3-1, the system input ports are:
CLK Clock signal (50Mhz oscillation signal on FALCON-E25TG Development Board)
RST Reset Signal
RS232_RX Serial input
SWITCHES 8-bit's switch input
The output ports are:
Rs232_tx Serial output
LEDS 8-bit LED output
Experiment 3 through the Development Board of the LED lamp to receive the signal sent by the switch, the toggle switch can be seen on the corresponding LED lamp on the light. In addition, the system's UART TX module sends data to the computer, and the system's UART RX module receives the data sent back by the computer.
The software program can correctly perform two loopback functions: in the LED lamp response switch settings, RS232 serial port receiving port response to the sending port serial data.
Once the experiment is complete, you will be able to understand how to design a simple embedded handler using Picoblaze.
Timing report Information
The timing report details why timing constraints fail and which paths are critical paths.
Timing Analyzer (Timing Analyzer) produces time series reports. The timing analyzer interface consists of three windows (Figure 3-2).
Use the hierarchical browser on the left (hierarchical Browser) to browse through the various parts of the report.
The path details (path Detail) window on the right includes a detailed description of the timing report.
The window at the top right shows the item selected in the hierarchical browser. The contents of the project are displayed in the Path Detail window.
Figure 3-2. The Timing Analyzer GUI
The Path Details window (Figure 3-3) includes detailed information about path latency, including:
slack: The difference between the constraint value (that is, the required path delay value) and the actual path delay value (the negative number indicates that the actual delay is greater than the constraint value, that is, the requirement is not met)
Source and end points of Path
Detailed composition list of path latency
Fan out of each network in the Delay path (fanout)
Path Delay sum
A percentage example of logical latency and network latency (this value indicates whether your latency path is reasonable).
Figure 3-3. Detailed Path Analysis
Steps
In Experiment 3, you will build a simple embedded system and improve performance with global timing constraints. The main steps are as follows:
1. Compilation of a Picoblaze project.
2. Enter the global timing constraint.
3. Enter the PIN constraint file.
4. Implement the design and analyze the time series report.
5. Write software and run HDL simulation.
6. Hardware validation.
Under the guidance of the Experimental Manual, you will complete the whole experiment step by step. If you are already familiar with the ISE software design process, you can skip the detailed instructions in one step and complete the experiment yourself.
Note: The symbol-guided paragraph is a description of the following steps in the paragraph, not an action step.
All steps in the handout that require the user to operate are guided by lowercase Arabic numerals.
Step 1: Compile the program template
Open the Time_const project in ISE Project Navigator, compile the source program PROGRAM.PSM, and generate program.vhd/v files for generating instruction memory.
1. Select start → program →xilinx ise design Suite 12.4→ISE design tools→project Navigator to enter the ISE Project Navigator environment.
2. Select File→open Project and point to the following directory, select Time_const.xise, open the project;
Verilog User: D:\ISE_Flows\ labs\ lab3\verilog\time_const
VHDL User: D:\ISE_Flows\ labs\ lab3\vhdl\time_const
3. Select start → program → accessories → command prompt, open the DOS command window, and use the CD command to point to the Assembly compiler directory:
The D:\ISE_Flows CD \labs\lab3\verilog\Assembler (Verilog user)
The CD d:\ISE_Flows\ labs\ lab3\vhdl\Assembler (VHDL user)
4. After entering the assembler directory, enter the: KCPSM3 PROGRAM.PSM command after the DOS command prompt symbol. When the command is complete, a number of files are generated under assembler, including the VHDL file (PROGRAM.VHD) and the Verilog file (PROGRAM.V), which are used for synthesis (integrated out of program memory ROM) and simulation.
5. Add the program.vhd/v file to the current project.
6. Click the top-level file loopback.vhd/v in the Project Sources window, and then double-click Check Syntax in the Synthesis-xst directory in the Processes window to see if there is a syntax error.
7. In the behavioral Simulation model, TESTBENCH.V/VHD is used as a simulation test platform for simulation. The time is 35000ns.
Note: After zooming in on the simulation waveform, you can see results similar to the following figure. Hexadecimal 55 represents the input signal of the switch, but there is no output on the LED light. In a later experiment, the code will be edited so that the LED light responds to the switch settings.
Figure 3-4 The switch position is not reflected on the LEDs
Step 2: Enter global timing constraints
Step 2 uses the constraint editor input cycle (PERIOD) and offset input/output (OFFSET in/out) constraints.
1. In the hierarchy window of the project, select the top-level file loopback.vhd/.v
2. In the Processes window under the Sources window, expand User constaraints and double-click Create tming Constraints (Figure 3-5). If there are no related constraint files in the current project directory, Project Navigator automatically creates a constraint file.
3. Click Yes to create a new UCF file: LOOPBACK.UCF, add it to the project.
4. Open the Constraint editor and select the lock domains under Constraint type (Figure 3-6).
Figure 3-5 Processes window of the project
Figure 3-6 Global Timing Constraint Editor
Set the cycle (PERIOD) constraint of the global clock signal CLK is 20ns
5. Double-click CLK under Unconstraints Lock to open the Lock Period dialog box. (Fig. 3-7)
6. Click OK to accept the default value (20ns).
Set the input bias constraint (OFFSET in) value of the global clock signal CLK is 7ns and the output bias constraint (OFFSET out) value is 7.5 ns. Save the constraint and exit the constraint editor.
7. Select the inputs below the Constraint Type window, double-click the blank area next to the Unconstraint port column to open offset in wizard, and leave the default settings to select Next. (Fig. 3-8)
8. Enter the constraint value of 7 ns in the blank area shown in Figure 3-9. Click OK. (Fig. 3-9)
9. Select the outputs below the Constraint Type window, double-click the blank area next to the Unconstraint port column to open offset in wizard, and leave the default settings to select Next. Enter the constraint value for 7.5 ns in the blank area shown in Figure 3-10. Click OK. (Fig. 3-10)
NOTE: The above constraints appear in the window in the lower-left corner of the constraint editor. (Fig. 3-10)
Figure 3-7 Clock Cycle dialog box
Figure 3-8 OFFSET in Wizard–clock Edge Page
Figure 3-9. OFFSET in Constraint dialog box
Figure 3-10. OFFSET out Constraint dialog box
Step 3: Enter pin position constraints
Step 3 Specifies the pin position for the top-level design I/O port. In this example, pin allocation is completed by directly copying the pin position in the given text file to the UCF file.
1. Expand User Constraints Double-click Edit Constraints (Figure 3-11) to open the UCF file.
Figure 3-11. Open the UCF file
2. Open D:\ Ise_flows \ lab3_ucf.txt file.
Figure 3-12. Pin position constraints
3. Copy the constraints in the Lab3_ucf.txt file to the UCF file.
4. Save and close the UCF file.
Step 4: Design timing Analysis
Implementation (implement) design. View the Post-map static Timing and Post-place of the 2 Route static Timing, analyze the design timing, and complete tables 1 and.
1. In the Processes window, expand implement Design to further expand the map.
If you don't see implement Design, verify that the loopback.vhd/.v file in the source window is selected.
2. Expand Generate post-map Static Timing.
3. Double-click Analyze Post-map static Timing to open the Static Time series Analysis tool (Timing Analyzer) to see the timing after the MAP.
Use the Post-map Static Timing reporting to check that the timing constraints in this example are feasible to avoid wasting place in the time of the
Locate the period constraint of clkfx_buf (DCM output) in the report and complete the problem ①.
If the time series constraint is not found in the Post-map static Timing, right-click Post-map static Timing to select Rerun all.
① problem-Complete the following table:
Chart 1 PERIOD constraint OFFSET in constraint OFFSET out constraint
Constraint
Post-map
4. Close the timing Analyzer window.
5. In the Processes window, expand the place of the place of the generate and the post-place of the Timing.
6. Double-click the post-place of the Timing Route static Timing, open the Static Time series Analysis Tool (Analyzer), view the timing after the Place&route, and complete the problem ②.
② problem-Complete the following table:
Chart 2 PERIOD constraint OFFSET in constraint OFFSET out constraint
Constraint
Post-p&r
Note: If the design does not meet the timing requirements after the place of the place of the following route, the constraint will need to be relaxed and implemented.
Step 5: Write a program to perform HDL emulation
With the actions of the previous steps, the hardware has met the timing requirements.
Step 5 Develop the Picoblaze assembler to meet the software requirements. The application template, including the definition of a large number of constants, has been given in the experiment. In this experiment, the user only needs to write simple code to complete three tasks (task), of which task #3 is the hardest. Experiment 5 only needs to complete Task #1,task #1完成开关和灯的回路测试.
It is important to note that each time you change the code, you must re-compile it to generate a new instruction memory.
1. Locate the PROGRAM.PSM in the assembler directory, write the code to complete the task #1, implement the read switch status and write to the LED light control port. Recompile once.
Tip: You only need to write two lines of code (refer to the KCPSM3 User manual). If you can't complete the code successfully, you can refer to the appropriate file in Labsolutions.
2. Go to behavioral Simulation mode and double-click Simulate behavioral model
3. Analyze the output waveform and close the simulation window when you are finished. (Fig. 3-13)
Figure 3-13. LEDs the setting signal of the response switch
Note: Binary value 10101010 (hexadecimal AA) appears in the Picoblaze switches input port and, after a delay, appears on the LED light output port. The simulation console (Sim console) Displays the simulation success information. (Fig. 3-14)
Figure 3-14. Observe information in the Simulation console
Step 6: Generate platform Flash PROM file
The FALCON-E25TG experimental board is equipped with Xilinx xcf02s/xcf04s platform Flash PROM. Step 6 uses the Impact tool to generate the Prom programming bitstream file (Intel formatted MCS format).
1. Double-click Generate programming file in the Processes window to generate the FPGA download bitstream file.
2. Start the Ipact tool, double-click the Create PROM file, and select each option as shown in the following figure. (Fig. 3-15)
Figure 3-15. Set up prom file formats
3. Click OK and finish to add Loopback.bit. When the dialog box appears, click No. This no longer adds additional FPGA bitstream files (1 Prom support configuring multiple FPGAs).
4. Double-click Generate file ... to generate PROM with bitstream files (MCS files), and if successful, you can see the "PROM File generation succeeded" message. (Fig. 3-16)
Figure 3-16. Generate MCS files
Step 7: Configure Prom to run the loopback experiment
Step 7 selects the prom and FPGA to be configured separately by selecting configuration mode, and the loopback program is tested on the Development Board.
1. Place the Development Board configuration mode selector switch in JTAG mode and turn on the Development Board power supply. (See FALCON-E25TG Board Manual)
2. Double-click Boundary-scan. This is shown in Figure 3-17.
Figure 3-17. Select Boundary Scan in impact
3. In the Boundary Scan window of impact, right-click the white area and select Initialize Chain.
4. When asked XC3S250E's configuration bitstream file, click Bypass.
5. Add the. mcs file to xcf02s/04s Platform Flash.
6. Right-click xcf02s/04s in the Jtag chain and select program. When the Programming Properties dialog box appears, click Ok>.
Note: If the program is unsuccessful, do not select the Erase before programming option, and then re-program.
7. Place the Development Board configuration mode selector switch in m-s mode, press the Prog button of the Development Board, or re-power, and the Development Board will configure the FPGA from the prom. Toggle the switch, you can see the corresponding LED lights on the light.
Conclusion:
This experiment uses Xilinx Constraints Editor to enter the global timing constraint to analyze the design timing by looking at Post-map and post-place of the Timing.
Timing constraints meet performance requirements. When implementing the first layout cabling of a tool, it is necessary to determine whether the timing constraints of the design are feasible. Timing performance can be estimated based on the Post-map Static Timing. Determine whether the timing requirements are met by looking at the post-place of the Route Static Timing.
Answer
The answer is not unique, and the results are related to factors such as the software version, patch version, and operating system used in the experiment.
① problem-Complete the following table:
Chart 1 PERIOD constraint OFFSET in constraint OFFSET out constraint
Constraint ~18.18 NS 7 NS 7.5 NS
Post-map ~8.85 NS ~7.115ns ~3.76 NS
② problem-Complete the following table:
Chart 2 PERIOD constraint OFFSET in constraint OFFSET out constraint
Constraint ~18.18 NS 7 NS 7.5 NS
Post-p&r ~13.78 NS ~6.89 NS ~4.54 NS
Experiment 4: Comprehensive technology Experiment
Target board: Falcon-E25TG
Introduced
Synthesis is an important link in the design process of FPGA/CPLD, and the advantages and disadvantages of the combined results directly affect the final layout wiring results. A good complex can make the user's design occupy the smallest physical area of the chip, and the fastest operating frequency, which is an important index to evaluate the advantages and disadvantages of the complex.
Synplify/synpliy Pro is a comprehensive tool produced by Synplicity company, which has attracted much attention for its comprehensive speed and excellent optimization. Xilinx Synthesis XST is a comprehensive tool embedded in the ISE software by Xilinx, although it is not prominent and functionally comprehensive compared to the industry's popular integrated tools such as Synplify/synpliy Pro, But Xilinx has the best knowledge of its FPGA/CPLD internal structure, so XST support for Xilinx devices is also the most direct and effective. More importantly, XST is embedded in the ISE, can be used directly, there will be no other costs.
Experiment 4 describes higher performance in the Xilinx FPGA design process by using the XST comprehensive options (attributes).
Goal:
After completing the experiment, you will be able to:
uses comprehensive options such as keep hierarchy and fanout to improve aggregate results and improve design performance.
Modify XST Comprehensive options, read the XST synthesis report, and judge the quality of the comprehensive results.
Steps:
This experiment consists of the following four parts:
View hardware and complete application software design
is combined according to the default values for the comprehensive option
Change Comprehensive options
View the combined results in RTL.
Under the guidance of the Experimental Manual, you will complete the whole experiment step by step. If you are already familiar with the ISE software design process, you can skip the detailed instructions in one step and complete the experiment yourself.
Note: The symbol-guided paragraph is a description of the following steps in the paragraph, not an action step.
All steps in the handout that require the user to operate are guided by lowercase Arabic numerals.
Step 1: View the composition of the design hardware and complete the application software
Open Ise™project Navigator and open the project file synth_lab.ise.
1. Select start → program →xilinx ise design suite 12.4→ise Design Tools→project Navigator, open Xilinx ISE.
2. Select File→open Project, select Synth_lab.xise, click Open
verilog User: D:\ISE_Flows\ labs\ lab4\verilog\synth_lab
VHDL User: D:\ISE_Flows\ labs\ lab4\vhdl\synth_lab
Update the PROGRAM.PSM file in Experiment 3 to complete task #2 (Task 2 Displays the words "Xilinx Rules" on the screen), which is compiled and added to the current project.
3. Open PROGRAM.PSM (in the Assembler subdirectory of this experiment) and add code to complete task #2.
Tip: At the top of the program, all ASCII characters are listed as constants. There are only two instructions (load and output) to display a single character. If the encoding is difficult, you can refer directly to the corresponding file in Labsolutions.
4. Open the Command window and browse to the assembler directory. The directory contains the PROGRAM.PSM file that you just encoded.
5. Enter the following command at the DOS prompt, the assembler compiles the application PROGRAM.PSM, and the resulting file is used to generate the instruction memory.
KCPSM3 PROGRAM.PSM
Note: If the PROGRAM.V (or. vhd) file is already in the current project. You can remove it before reloading the newly generated file into the project.
Step 2: Synthesize and implement according to the default values
Synthesis of top-level file Loopback.v/.vhd
1. Click Loopback.v/.vhd
2. In the Processes window, double-click synthesize-xst
Review the comprehensive report and answer questions ① and ② in the Sources window.
3. In the Design Overview window, click View Synthesis
4. Using the Find tool at the bottom of the page, enter timing Summary and press ENTER.
① write down the estimated clock frequency (for comparison with later results):
____________________________
5. Enter device utilization in Find and click Find Next.
② Write down Resource usage:
Slices
Slice Flip Flops
4 input LUTs
Iobs
Brams
Global Clocks
DCMs
6. Closure of the comprehensive report.
7. In the Process window, expand implement Design and expand place in the place of the place.
Double-click Analyze Timing/floorplan Design (planahead), the Web table view is opened, and you can observe it through tools→show hierarchies loopback Hierarchical relationships with two modules of primitives (figures 4-1 and 4-2)
8. Exit Planahead.
Figure 4-1. Nets and Primitives View
Figure 4-2. A flat view of the physical layer, the network table, and the design
Step 3: Change the comprehensive options
In general, HDL Design is a collection of modules at all levels. Maintaining the hierarchy of the module or leveling the hierarchy (flattened) is beneficial to the design to some extent and requires specific analysis of specific problems. For FPGAs, if you can pay attention to the synchronization design techniques, choose to maintain the design of the hierarchy to improve performance, easy to debug analysis. In some cases, especially in the asynchronous circuit design, the hierarchical structure of the leveling design can allow the comprehensive tool to optimize the design better.
Sometimes, the effect of synthesizing by default value is not good. Designers need to understand the common comprehensive options, flexible application.
Change the comprehensive options, as shown in the following figure, and then synthesize them once.
keep Hierarchy:yes
Figure 4-3. Synthetic attributes
1. In the Processes window, right-click synthesize select Properties.
2. In Synthesis Options, set Keep hierarchy to Yes, as shown in Figure 4-3.
Note: If you select Keep hierarchy (in fact, a comprehensive constraint is specified), the implementation tool retains the design hierarchy throughout the implementation process (referring to VHDL entities or Verilog modules, rather than the macros that was extrapolated during the synthesis process).
3. Click OK and re-synthesize.
4. Open the synthesis report, enter the timing Summary in the find below the page, press ENTER to find the relevant Time series summary section, answer the following question.
③ recorded the estimated clock frequency and observed changes in system performance.
__________________________
5. Enter device utilization in the find below the page, click Find Next, and find the Resource Utilization section to answer the following question.
④ the utilization of resources is recorded in the following table:
Slices
Slice Flip Flops
4 input LUTs
Iobs
Brams
Global Clocks
DCMs
6. Enter Fanout in Find and click Find Next.
⑤ which NET has the largest fanout? Which data path does it belong to?
_______________________________
Fanouts is too big to cause cabling problems, and by xst constraints, you can limit the number of fanout. This restriction does not require special consideration, especially when its number is less than 30.
7. Right-click synthesize–xst Select Properties.
8. In the Xilinx Specific options option, enter the max fanout number 50. Click OK. (Fig. 4-4)
9. Double-click Synthesize–xst and re-synthesize.
10. Open the synthesis, find fanout, and answer the question below.
⑥ which net Fanout is the largest and which data path does it belong to?
___________________________
11. In the synthesis, find timing summary and answer the following questions.
What is the maximum clock frequency for ⑦ design?
___________________________
Figure 4-4. Xilinx Specific Options
12. In the Processes window, expand implement design and double-click Analyze Timing/floorplan Design (planahead) below place in the place.
13. View the design hierarchy (hierarchy) through Tools→show hierarchy. (Fig. 4-5 and fig. 4-6)
Figure 4-5. Network table Design view
Figure 4-6. Hierarchical view of the design
Step 4: Download and system testing
Step 4 produces the FPGA configuration Bitstream file and configures the FPGA through the JTAG download line.
1. Configure the configuration mode selection jumper on the Falcon Development Board and select the configuration mode as JTAG.
2. Connect the download line and power the Falcon board.
3. Open the HyperTerminal created in Experiment 3 (the baud rate is 9600).
4. Double-click Generate programming to generate a bitstream file.
5. Expand configure target device and double-click Manage Configuration project (impact)
6. When the Impact dialog box appears, select Boundary-scan Mode, click Next, and then click Finish.
7. The prompt box that appears indicates that the impact software detects two devices and clicks OK.
8. Assign the Loopback.bit file to the XC3S250E device (the first device in the JTAG chain) and select bypass for the platform Flash Prom device.
9. Right-click the xc3s250e device and select Program.
Note: After the download is successful, you should see the words "Xilinx Rules" in the HyperTerminal window.
10. Toggle the switch, on the Falcon board can see the LED light lit.
Conclusion
The comprehensive option is actually the constraint imposed on the synthesis, with different comprehensive options, and the performance of the integrated system is different. Understanding mastering the comprehensive availability of options can help improve system design performance.
Answer
① writes down the estimated clock frequency (for comparison with later results).
Minimum period (Verilog): one ns (Maximum Frequency: ~107 MHz) Minimum period (VHDL): ~8.15 NS (Maximum Frequency: ~122 MH Z
Note: The experimental results are related to the PC system you are using
② Write down Resource usage:
Slices 163 (Verilog)/160 (VHDL)
Slice Flip Flops 147 (Verilog)/147 (VHDL)
4 Input LUTs 303 (Verilog)/299 (VHDL)
IOBs 21 （Verilog and VHDL）
Brams 1 (Verilog and VHDL)
Global Clocks 2 (Verilog and VHDL)
DCMs 1 (Verilog and VHDL)
③ record estimated clock frequency to observe system performance changes
Minimum period (Verilog): ~9.76 NS (Maximum Frequency: ~102 MHz)
Minimum period (VHDL): ~8.68 NS (Maximum Frequency: ~115 MHz)
Note: The experimental results are related to the PC system you are using
④ record resource utilization in the following table
Slices 167 (Verilog)/163 (VHDL)
Slice Flip Flops 147 (Verilog)/147 (VHDL)
4 Input LUTs 303 (Verilog)/298 (VHDL)
Iobs (Verilog and VHDL)
Brams 1 (Verilog and VHDL)
Global Clocks 2 (Verilog and VHDL)
DCMs 1 (Verilog and VHDL)
⑤ which NET has the biggest fanout? Which data path does it belong to?
Verilog
LUT3:I2->O (Operand_select_mux_1 (port_id<1>)) with Fanout of 84
Data path:my_kcpsm3/reg_loop_register_bit_1 to Transmit/buf_0/register_bit_3
Vhdl
LUT3:I2->O (Reg_loop.operand_select_mux (port_id<0>)) with Fanout of 84
Data Path:my_kcpsm3/reg_loop.register_bit to Transmit/buf/count_width_loop.register_bit
⑥ which net Fanout is the largest and which data path does it belong to?
Verilog
LUT3:I2->O (Operand_select_mux_1 (port_id<1>)) with Fanout of 43
Data path:my_kcpsm3/reg_loop_register_bit_1 to Transmit/buf_0/register_bit_3
Vhdl
LUT3:I2->O (Reg_loop.operand_select_mux (port_id<0>) with Fanout 43
Data Path:my_kcpsm3/reg_loop.register_bit to Transmit/buf/count_width_loop.register_bit
What is the maximum clock frequency for ⑦ design?
Minimum period (Verilog): ~11.7.ns (Maximum Frequency: ~85 MHz)
Minimum period (VHDL): ~10.6 NS (Maximum Frequency: ~94 MHz)
Note: The experimental results are related to the PC system you are using
Experimental 5:IP nuclear generator system experiment
Target board: Falcon-E25TG
Introduced
Experiment 5 generates IP cores through the Xilinx core generator™ system and embeds them into user design.
Goal
When the experiment is complete, you will be able to acquire the following abilities:
generates an IP core with Xilinx core generator
of IP core to HDL design
Behavior Simulation of HDL design with IP kernel
Design through Development Board hardware verification
Steps
Experiment 5 uses the core generator generator to generate the program memory of Picoblazer, and picoblaze it into the application system, and finally completes the hardware verification on the FALCON-E25TG Development Board.
View hardware design, build program memory ROM initialization file
Generator Memory IP kernel (blockram)
Process Memory IP kernel to application system
The behavior simulation of application system
Hardware validation on the Development Board
Under the guidance of the Experimental Manual, you will complete the whole experiment step by step. If you are already familiar with the ISE software design process, you can skip the detailed instructions in one step and complete the experiment yourself.
Note: The symbol-guided paragraph is a description of the following steps in the paragraph, not an action step.
All steps in the handout that require the user to operate are guided by lowercase Arabic numerals.
Step 1: View the hardware design, build the program memory ROM initialization file
Start the Ise™project Navigator and open the project file
1. Select start → program →xilinx ise design suite 12.4→ise Design Tools→project Navigator, open Xilinx ISE 12.4.
2. Click File→open Project, select Coregen.xise, and click Open.
verilog Users: Browse d:\ Ise_flows \ labs\ Lab5\verilog\coregen
VHDL Users: Browse d:\ Ise_flows \ labs\ Lab5\vhdl\coregen
Browse the design and you can see a red question mark mark. Using the program of the previous experiment, complete the task #3, and the assembly generates a parameter file with the. Coe (Coe used to initialize the program memory ROM).
3. In D:\ ISE_Flows\Labs\lab5\vhd (Verilog) \assembler Open the assembly application PROGRAM.PSM in the directory.
4. Write the program code, complete the task #3, tasks 3 through the HyperTerminal to display the content entered from the keyboard.
Note: Refer to the comments in your code when writing your code. If you have difficulty writing code, refer to the appropriate content in solutions.
5. Open the DOS Command Prompt window and enter the following command at the command prompt:
KCPSM3 PROGRAM.PSM
Note: The assembler will produce included. Several files, including the Coe file. In the use of core generator to generate instruction memory ROM. The Coe file is used to initialize ROM data.
Step 2: Generator memory IP kernel (blockram)
Create a source file of type IP Core, named program. This source file (IP Core) will use Blockram.
1. In the Processes window, select Project→new Source.
2. In the New Source dialog box, select IP (Coregen architecture Wizard) and enter the program in the file Name blank. (Fig. 5-1)
Figure 5-1. New Source dialog box
3. Click Next.
4. In the Select Core Type dialog box, expand Memories Storage Elements, expand Rams ROMs, and select Block Memory Generator v4.3. (Fig. 5-2)
Figure 5-2. Select the Kernel Type dialog box
5. Click Next and click Finish.
Note: After 1-2 minutes, the CORE generator™ system interface opens.
6. As shown in Figure 5-3, set the dual Port Block memory parameter according to the following parameters, click Next.
Component Name: Program
Storage Internal type: Dual Port ROM
Memory Size: 1024 x 18
Figure 5-3. Block Memory Options
7. Set the port a parameter as shown in Figure 5-4 and click Next.
read width:18
read depth:1024
operating Mode:write First
enable:always Enabled
Figure 5-4. Port A Options
8. Click Load Init file to select the Program.coe file you just generated. (Fig. 5-5)
Figure 5-5. Initialize memory with program
Note: If the. Coe file format is not compatible (the specified file is red), you can use the text editor to modify the. Coe file, keep only the file rows (2) that begin with Memory_initialization, and then rerun the load Init file step.
9. Click the Show button, select Memory_initialization_vector from the drop-down box, and you can observe the initialization data of the program memory, as shown in Figure 5-6, and then click OK. When the FPGA configuration is complete, these initialization data is loaded into the Blockram as the program memory.
Figure 5-6. Block RAM Initialization Content
10. Click Next and click Finish.
Note: The Program.xco file should have been automatically added to the current project.
Step 3a: Example program memory IP kernel into the application system (Verilog)
Note: VHDL users do not do this step, please skip directly to step 3b
The program memory ROM kernel generated in step 2 is analyzed.
1. In the Sources window, double-click LOOPBACK.V and the Loopback.v file is opened in the right window.
2. Select program in the hierarchy of the Project window, and then double-click View HDL instantiation Template (Figure 5-7a)
Figure 5-7a. Examples of templates
3. Copy and paste the annotation statement of the sample template content to the loopback.v file under "//instantiate the ROM block here".
4. Edit the illustrated statement in the LOOPBACK.V file as follows to complete the signal connection:
Program My_program (
. Clka (Clk55MHz),
. Addra (Address),
. Douta (instruction),
. CLKB (1 ' b0),
. ADDRB (A ' b0000000000),
. DOUTB ());
5. Select File→save.
Step 3b: Example program memory IP kernel into the application system (VHDL)
Note: Verilog users do not do this step, please skip directly to step 4
The program memory ROM kernel generated in step 2 is analyzed.
1. In the Hierarchy window, double-click Loopback.vhd and the source file is opened in the right window.
2. Select program in the hierarchy of the Project window, and then double-click View HDL instantiation Template (Figure 5-7b)
Figure 5-7b. Language Templates
3. Copy and paste the component declaration content into the Loopback.vhd file in the sample module. Paste the annotation statement into the Loopback.vhd file--insert component declaration for Pro.
4. Copy and paste the component instantiation content into the Loopback.vhd file in the sample module. Paste the annotation statement into the Loopback.vhd file-insert component instantiation for program here.
5. Edit the illustrated statement in the Loopback.vhd file as follows to complete the signal connection:
My_program:program
Port Map (
Clka => Clk55MHz,
Addra => Address,
Douta => Instruction,
Clkb => ' 0 ',
ADDRB => "0000000000",
DOUTB => Open);
6. Select File→save Save.
Step 4: Simulate the behavior of the application system
Check the Testbench file to understand what has changed.
1. In the Hierarchy window, double-click TESTBENCH.V/.VHD (if not, add it yourself by referring to the preceding steps).
To view the features of Testbench, note the following comments section:
the Testbench Toggles switches
waits for some lock cycles
checks the LEDs to see if they match the switch settings
2. In the Hierarchy window, select Program.xco.
3. In the Processes window, expand Coregen and double-click View VERILOG/VHDL functional Model.
Note: This file comes from the Xilinxcorelib simulation Experiment Model Library, which is automatically called when behavioral simulation is performed within the ISE. (For VHDL users, if the simulation model file does not appear, right-click View VERILOG/VHDL functional Model, select Open Without Updating)
Run behavior simulation with a simulation time of 50000 NS. Observe the simulation waveform and verify that the IP core has been properly embedded.
4. In the design window, select Simulation and select Testbench.v/.vhd.
5. In the Processes window, expand Isim Simulator and double-click Simulate Behavioral Model.
6. Enter 50000NS in simulation run time.
7. Click OK.
8. Double-click Simulate Behavioral Model.
9. Observe the simulation waveform and analyze whether the change of the LED light port signal can reflect the setting of the switch port signal.
Step 5: Hardware validation on the Development Board
Open HyperTerminal. Generate FPGA configuration bitstream files and download them to the lab board.
1. According to experiment 2, introduce a new super terminal, set the Super terminal baud rate of 9600, connect the development Board, turn on the power supply.
2. In the Processes window, expand Configure Target Device and double-click Manage Configuration Project (IMPACT).
3. When the impact window opens, the window shows two devices detected in the JTAG chain, click OK.
4. Assign loopback.bit files to the Spartan-3 xc3s25e device, and the rest select Bypass.
5. Right-click Spartan-3 xc3s250e, select program, click OK, will be configured with the JTAG download line FPGA.
6. After the download is successful, you will see "Xilinx rules!" in the HyperTerminal window , enter any character on the keyboard and observe the display in the HyperTerminal window.
Figure 5-9. Observe the output in the HyperTerminal window
Conclusion
Experiment 5 through the core generator™system generator memory IP kernel, and the example into the design. Veo and VHO files are examples of modules that can be used to easily automate the operation of IP cores. V and. VHD files are simulation modules that support the behavior simulation of IP cores.
Experimental 6:chipscope Debugging experiment
Target board: Falcon-E25TG
Introduced
Experiment 6 is on-chip debugging by embedding the Ila/icon kernel in the design.
Chipscope Pro (Online logic Analyzer) has the function of a traditional logic analyzer and is an in-chip signal analysis tool for Xilinx FPGA. Chipscope Pro reads the FPGA signal online and in real time through the JTAG port.
Depending on the trigger conditions set by the user, Chipscope Pro can save the signal that the user cares about in real time to the unused in-chip blockram, and then transfer it through the JTAG port to the analysis tool running on the computer, showing the time series waveform on the computer screen. The Chipscope Pro tool makes the FPGA no longer a black box, using Chipscope Pro to easily observe all the signals inside the FPGA, which is very beneficial for the internal logic debugging of the FPGA.
Use Chipscope Pro to observe the advantages of FPGA internal signals as follows:
Low cost: Just a JTAG cable and Chipscope Pro software.
Flexibility: The number of observed signals and storage depth is determined by the number of Blockram remaining in the device, and the more remaining Block-ram, the greater the number of observable signals and storage depth.
Easy to use: Chipscope Pro is able to read design network tables (NGC, EDF, or edn files) and automatically insert itself (Web tables) into the original Design network table. Users can easily select the signal to be observed and can set complex trigger conditions. Chipscope Pro uses only a small number of lookup table resources and register resources, with little impact on the original design.
Goal
After completing the experiment, you will be able to:
creates a Chipscope-pro source file in the Ise.
uses Chipscope-pro to create ILA and ICON cores and to visualize them in the design.
Use Chipscope Analyzer to set trigger options.
Download the FPGA configuration bitstream file in Chipscope Analyzer.
runs the on-chip debugging function to observe the waveform in Chipscope Analyzer.
Steps:
Experiment 6 modifies the Picoblaze software application and uses Chipscope-pro to run on-chip debugging.
The experiment consisted mainly of 4 steps:
Add Chipscope Engineering files to current design
Modify the ILA parameter and connect the signal
Configuration Chipscope Analyzer software, update design
run on-chip debugging functions.
Under the guidance of the Experimental Manual, you will complete the whole experiment step by step. If you are already familiar with the ISE software design process, you can skip the detailed instructions in one step and complete the experiment yourself.
Note: The symbol-guided paragraph is a description of the following steps in the paragraph, not an action step.
All steps in the handout that require the user to operate are guided by lowercase Arabic numerals.
Design Overview:
Experiment 6 uses Chipscope-pro to insert the icon core and Ila core into the current design, and the trigger port of the ILA kernel is the feedback of the UART_RX and UART_TX module signals in the design. Next, with HyperTerminal text input, you can set up triggers to capture data. When the buffer is full, you should see the results on the chipscope.
Step 1: Add Chipscope Engineering files to the current design
Open Ise™project Navigator and open the project file.
1. Select start → program →xilinx ise design suite 12.4→ise Design Tools→project Navigator, open Xilinx ISE.
2. Select File→open Project
verilog User: Browse to D:\ISE_Flows\ labs\lab6\ verilog\chipscope
VHDL Users:: Browse to D:\ISE_Flows \labs\lab6\ vhdl\chipscope
3. Select Chipscope.xise Click Open.
Create a Chipscope-pro project through Project Navigator.
4. Select Projectnew Source, open the Create Xinyuan file dialog box, click Chipscope Definition and Connection file, enter the file name Loopback_cs. Click Next. (Fig. 6-1)
Figure 6-1. Xinyuan file dialog box
5. In the Sources window, select the loopback file as the source file, click Next, and then click Finish. The Chipscope-pro source file is added to the sources of the Project window. (Fig. 6-2)
Figure 6-2. Add Chipscope definition and Connection (. CDC)
Step 2: Modify the ILA core parameter and connect the signal
Insert ICON and ILA cores into the current design network table. Connect the output of the accumulator to the input of the trigger and the ILA core.
1. Double-click the LOOPBACK_CS.CDC file to open the Chipscope-pro project (Inserter interface). (Fig. 6-3)
Figure 6-3. Chipscope-pro Core Inserter
Note: The Chipscope-pro project holds related source files, target files, kernel parameters, and kernel settings.
2. Click Next, click the new ILA Unit button in the lower-right corner, or select the new ILA Uni command under the Edit menu. Note that U0:ila appears in the upper-left window. (Fig. 6-4)
Figure 6-4. Embed the new Integrated Logic Analyzer (ILA) unit
3. Click Next to start setting the trigger parameters.
Each ILA or ILA/ATC core has 16 separate trigger ports that can be set separately. The trigger port is the bus structure, which consists of a separate signal or a bit bit ranging from 1 to 256. Each trigger port can connect 1 to 16 matching units.
Each matching unit is actually a comparator, connected to a trigger port, respectively, to detect events that trigger the port. One or more matching units are combined to form a complete trigger condition event that is used to control data capture. The ILA and ILA/ITC cores support 6 different types of matching units, and different matching units perform different comparison functions.
In Experiment 6, the ILA core is set by some UART control signals.
4. After setting the ILA trigger parameter according to the following data, click Next. (Fig. 6-5)
Trigger input and Match unit settings:
number of input Trigger Ports:3
Trigger Port Trigger Width # match Units counter Width match Type
TRIG0 1 1 Disabled Basic
TRIG1 1 1 Disabled Basic
TRIG2 1 1 Disabled Basic
Trigger Condition Settings:
enable Trigger Sequencer: Selected (used to specify the order in which events can be triggered)
max of Sequencer Levels:2
Storage Qualification Condition Settings:
enable Storage Qualification: Selected (for specifying which data to store)
Figure 6-5. Specifying Trigger Parameters
The maximum value of the sampled data that the ILA core can store in the sampling buffer is called the storage depth (data depth). Storage depth and data width are mutually constrained, depending on the size of the remaining blockram in the design.
5. Set the options below and click Next. (Fig. 6-6)
data depth:512
sample on:rising Lock Edge
data Same as Trigger port:unchecked
data Width:8
Figure 6-6. Specify Trigger Parameters
Net Connections connects the ILA or ILA/ATC nuclei to the selected signal. Users need to specify clocks, triggers, and data connections, respectively. No connection will display red. (Fig. 6-7)
Figure 6-7. Unconnected Net Connections
6. Click the Modify Connections button to appear in the Select Net interface. (Fig. 6-8)
Figure 6-8. Net Connections
The Select Net dialog box provides a simple graphical interface that connects the selected observation signal to the ILA or ILA/ATC core. By using the structure/nets of the upper-left window, you can browse the hierarchy of the current design, making it easy to select the signals you want to observe.
7. Select the Lock Signals tab under NET selections, click the CL signal in the list of networks on the left, and then click the Make Connections button in the lower right corner to connect the Clk55mhz signal to the clock port of the ILA core. (Fig. 6-9)
Figure 6-9. Connecting clock signals
8. Click the Trigger Signals tab to connect three trigger ports. (Fig. 6-10)
tp0:data_present (the signal indicates that the data appears in the UART_RX module)
tp1:read_from_uart (This is the input signal for the UART_RX module, indicating that the read operation will occur)
tp2:write_to_uart (This is the input signal for the UART_TX module, indicating that the write operation will occur)
Figure 6-10. Even contact with the starter port
9. Click the Data Signals tab to connect the Picoblaze data output port Out_port to the ILA kernel data port, as shown in Figure 6-11, and then click OK.
Figure 6-11. Connect the Picoblaze output port
10. Note that the lock port, the trigger port, and the data port under the Net Connections window all display black, indicating that all connections are valid. Click Return to Project Navigator to save the file. (Fig. 6-12)
Figure 6-12. Connect design with ILA core
Step 3: Configure Chipscope Analyzer software to update the design
The Chipscope-pro Analyzer tool is connected to the ILA core via the icon core. You can configure the FPGA through Chipscope-pro Analyzer, select the trigger conditions, set up the console, observe the capture data, and so on. There are several ways to work with captured data.
1. In the Hiersrchy window, click the top-level file Loopback.v/vhd, double-click Analyze Design Using chipscope in the Processes window, and open the Chipscope Analyzer tool.
2. Connect the FALCON-E25TG board download line and turn on the power supply on the board.
3. Click the open cable/search JTAG Chain button in the upper-left corner of the Chipscope Analyzer window. (Fig. 6-13)
Figure 6-13. Establish a JTAG connection
4.2 devices can be found in Jtag chain, namely spartan-3e xc3s250e and platform Flash xcf02s or xcf04s, click OK.
5. Right-click xc3s250e and select Configure.
6. Click Select New File, browse to the current project catalog, select Loopback.bit, and notice that. cdc files are also added to the project at the same time, click OK.
The Chipscope Pro Analyzer interface consists of four parts.
Each chipscope Pro ILA, ILA/ATC, and IBA cores have their own trigger settings window, which provides graphical interface setting triggers. The trigger structure of each Chipscope Pro core can be modified in real time without the need for a re-integration implementation. The trigger structure has three elements:
match Functions: Defines the comparison value for each matching cell.
trigger Conditions: Defines the full trigger condition based on a binary equation or a sequence of one/more matching functions.
capture Settings: Defines the number of sampled data, the number of sampling windows, and the position of triggers in the sampling window.
Experiment 6 Sets the trigger at the Picoblaze output to capture the text data it emits.
Figure 6-14. Chipscope Analyzer window
7. Specify the following Match Units. (Fig. 6-15)
radix: Binary
m0:triggerport0 (data_present): Value 1
m1:triggerport1 (Read_from_uart): Value 1
m1:triggerport1 (Write_to_uart): Value 1
Figure 6-15. Set up matching units
8. Click the area under Trigger condition equation, select the options below the Sequencer tab, generate the M0→M1 expression, and then click OK.
Figure 6-16. Trigger condition equation
9. Click on the area near storage qualification, select and equation, click M2, click OK. In this way, when the write_to_uart signal becomes high-power, it will enable the capture of the data store.
Figure 6-17. Storage Qualification equation
Step 4: Run the On-chip debugging feature
Step 4 Import a. cdc file. Run the on-chip debugging function to observe the debugging results.
1. Perform the following operation to generate a bus consisting of a 8-bit out_port signal.
selects signals, from out_port<0> to out_port<7>.
Right-click these signals, select Add to Busnew bus, and create the bus output_port.
Figure 6-18. Create a new Output_port bus
2. Set the data cache depth (depth): 16. (Fig. 6-19)
Figure 6-19 Selecting data Cache depth
3. Click the Apply Settings and Arm Trigger button. (Fig. 6-20)
Figure 6-20. Apply Settings and Arm Trigger
4. Enter "Xilinx #1 fpga!" at HyperTerminal to observe the information in Chipscope Analyzer. Right-click Out_portbus Radix, select the 馎 scii format. (Fig. 6-21)
Figure 6-21. Verify capture Results
Conclusion
Embedded ila nuclei and ICON cores into Picoblaze application design, set trigger conditions in Chipscope Analyzer, run on-chip debugging, and analyze waveforms in Chipscope-pro Analyzer.
Falcon-E25TG型FPGA开发平台 ISE流程实验手册 Falcon-E25TG型FPGA开发平台 ISE流程实验手册
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