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以下面程序为主程序，添加校园定时打铃功能，可以同时随意设定多个打铃时间Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsugned.all;
entity Clock is
port( mode,set,clr,clk:in std_logic;seg7,segctr:out std_logic_vector(7 downto 0));
end entity;
ARCHITECTURE arch OF Clock IS
Type st is(s0,s1,s2,s3);
signal state: st;
signal Hour, Min,Sec: integer range 0 to 59;
signal BCDH,BCDM,BCDS:std_logec_vector(7 downto 0);
signal segDat:std_logic_vector(3 downto 0);
signal blink:std_logic_vector(2 downto0);
signal blink_clk:std_logic;
signal set_reg:std_logic;
component BCD
Port(DataIn :in integer range 0 to 59;
BCDOut :out std_logic_vector(7 downto 0)
);
end component;
BEGIN
Process(mode,clr)
begin
if(clr=’1’) then
state<=s0;
else
if(mode’event and mode=’1’)then
case state is
when s0=>state<=s1;
when s1=>state<=s2;
when s2=>state<=s3;
when s3=>state<=s0;
end case;
end if;
end if;
end process;
process(clk)
variable blink_cnt: std_logic_vectot(7 downto 0);--(13 downto 0);
begin
if (clr=’1’) then
blink_clk<=’0’;
blink_cnt:=(others =>’0’);
else
if(clk’event and clk=’1’) then
if (blink_cnt=”01100011”) then
blink_cnt:=(others=>’0’) ;
blink_clk<=not blink_clk;
else
blink_cnt:=blink_cnt+1;
end if;
end if;
end if;
end process;
process(state,blink_clk)
begin
case state is
when s0=>blink<=”000”;
when s1=>blink<=(2=>blink_clk, others=>’0’);
when s2=>blink<=(1=>blink_clk, others=>’0’);
when s3=>blink<=(0=>blink_clk, others=>’0’);
end case;
end process;
process(clk,state,clr)
variable clk_cnt:std_logic_vector(9 downto 0);
begin
if(clr=’1’) then
Hour<=0;Min<=0;Sec<=0;
clk_cnt:=(others =>’0’);set_reg<=’0’;
else
if(clk’event and clk=’1’) then
case state is
when s0=>
if (clk_cnt=”1111100111”) then
clk_cnt:=(others=>’0’);
if (Sec=59) then
Sec<=0;
If(Min=59) then
Min<=0;
If(Hour=23) then
Hour<=0;
else Hour<=Hour+1;
end if;
else Min<=Min+1;
end if;
else Sec<=sec+1;
end if;
else clk_cnt:=clk_cnt+1;
end if;
when s1=>
if(set=’1’) then
if set_reg=’0’ then set_reg<=’1’;
if (Hour=23) then Hour<=0;
else Hour<=Hour+1;
end if;
end if;
else set_reg<=’0’;
end if;
when s2=>
if(set=’1’) then
if set_reg=’0’ then set_reg<=’1’;
if (Min=59) then
Min<=0;
else Min<=+1;
end if;
end if;
else set_reg<=’0’;
end if;
when s3=>
if(set=’1’) then
if set_reg=’0’ then set_reg<=’1’;
if (Sec=23) then
Sec<=0;
else Sec<=Sec+1;
end if;
end if;
else set_reg<=’0’;
end if;
end case;
end if;
end if;
end process;
HBCD:BCD
port map(Hour,BCDH);
HBCD:BCD
port map(Min,BCDM);
HBCD:BCD
port map(Sec,BCDS);
process(clk,clr)
variable cnt:std_logic_vector(2downto 0);
begin
if(clr=’1’) then
cnt:= (others =>’0’);
segCtr<=(others =>’0’);
else
if(clk’event and clk=’1’) then
cnt:=cnt+1;
case cnt is
when”000” =>
segDat<=BCDH(7 downto 4) or (blink(2)&blin(2)&blink(2)&blink(2));
segctr<=”10000000”;
when”001” =>
segDat<=BCDH(3 downto 0) or (blink(2)&blin(2)&blink(2)&blink(2));
segctr<=”01000000”;
when”010” =>
segDat<=”1010”;
segctr<=”00100000”;
when”011” =>
segDat<=BCDM(7 downto 4) or (blink(1)&blin(1)&blink(1)&blink(1));
segctr<=”00010000”;
when”100” =>
segDat<=BCDM(3 downto 0) or (blink(1)&blin(1)&blink(1)&blink(1));
segctr<=”00001000”;
when”101” =>
segDat<=”1010”
segctr<=”00000100”;
when”110” =>
segDat<=BCDS(7 downto 4) or (blink(0)&blin(0)&blink(0)&blink(0));
segctr<=”00000010”;
when”111” =>
segDat<=BCDS(3 downto 0) or (blink(0)&blin(0)&blink(0)&blink(0));
segctr<=”00000001”;
end case;
end if;
end if ;
end process;
process(segDat)
begin
case segDat is
when ”0000” => seg7<=”11111100”;
when ”0001” => seg7<=”01100000”;
when ”0010” => seg7<=”11011010”;
when ”0011” => seg7<=”11110010”;
when ”0100” => seg7<=”01100110”;
when ”0101” => seg7<=”10110110”;
when ”0110” => seg7<=”10111110”;
when ”0111” => seg7<=”11100000”;
when ”1000” => seg7<=”11111110”;
when ”1001” => seg7<=”11110110”;
when ”1010” => seg7<=”00000010”;
when others => seg7<=”00000000”;
end case;
end process;
end arch;
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