求VHDL达人帮忙翻译
begin----------------------------------------------------------------------------
-- 8 registers of 16 bits each
----------------------------------------------------------------------------
seldreg_s <= w & seldreg;
process (clk,reset)
begin
if reset='1' then
axreg_s <= (others => '0');
cxreg_s <= (others => '0');
dxreg_s <= (others => '0');
bxreg_s <= (others => '0');
spreg_s <= (others => '0');
bpreg_s <= (others => '0');
sireg_s <= (others => '0');
direg_s <= (others => '0');
elsif rising_edge(clk) then
if (wrd='1') then
case seldreg_s is
when "0000" => axreg_s(7 downto 0)<= dibus(7 downto 0); -- w=0 8 bits write
when "0001" => cxreg_s(7 downto 0)<= dibus(7 downto 0);
when "0010" => dxreg_s(7 downto 0)<= dibus(7 downto 0);
when "0011" => bxreg_s(7 downto 0)<= dibus(7 downto 0);
when "0100" => axreg_s(15 downto 8) <= dibus(7 downto 0);
when "0101" => cxreg_s(15 downto 8) <= dibus(7 downto 0);
when "0110" => dxreg_s(15 downto 8) <= dibus(7 downto 0);
when "0111" => bxreg_s(15 downto 8) <= dibus(7 downto 0);
when "1000" => axreg_s <= dibus; -- w=1 16 bits write
when "1001" => cxreg_s <= dibus;
when "1010" => dxreg_s <= dibus;
when "1011" => bxreg_s <= dibus;
when "1100" => spreg_s <= dibus;
when "1101" => bpreg_s <= dibus;
when "1110" => sireg_s <= dibus;
when others => direg_s <= dibus;
end case;
end if;
end if;
end process;
由于是初学VHDL，要做毕业设计。以上这段看不太懂，是什么意思?是赋值么? 在不同的状态，将DIBUS的DATA赋值给不同的寄存器 代码中"reset " 起到异步清零的作用，"wrd"是同布置数的功能。哪那个为1,就执行哪个。
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