在VHDL中, 定义为SIGNAL的量起到什么作用？什么时候需要定义这个量？
在VHDL中, 定义为SIGNAL的量起到什么作用？什么时候需要定义这个量？下面的程序ARCHITECTURE EXER2_ARCH OF EXERCISE2 IS
SIGNAL TEM: STD_LOGIC;
BEGIN
TEM<=PIN50 AND PIN51;
PIN8 <=TEM;
END EXER2_ARCH;
和如下的程序有何区别？
ARCHITECTURE EXER2_ARCH OF EXERCISE2 IS
BEGIN
PIN8<=PIN50 AND PIN51;
END EXER2_ARCH;
答：If PIN8 is declared in your port list,the 2 examples are identical.From a hardware design's perspective,you can think of a vhdl "signal" as an electrical signal.So basically you can declare every object as "signal".>From a simulation's perspective,there is a fundamental difference between "signal" and "variable" in vhdl.A variable is nothing more than an object that holds a value.A variable assignment occurs instantly in a vhdl simulation.Also,a variable can only exist within a process,so it cannot transfer values across processes.A signal,on the other hand,has a history of values.Whenever a signal assignment occurs,the vhdl simulator schedules an event to update the signal value after a certain period of simulation time - the signal does not get this new value instantly in the simulation time domain.Also,a signal can exists outside processes.Sounds complicated,but for most of the time you can simply use vhdl "signal" in your hardware design.（参考译文：如果在端口表中声明了PIN8, 这两个示例是一样的. 从硬件设计的角度看, 可以将vhdl "signal"视为电子信号. 因此, 基本上可以将每个对象声明为“signal”. 从仿真角度看, vhdl中的"signal" 与 "variable"是根本不同的. 变量只不过是拥有值的对象. 变量分配即时出现在vhdl仿真中. 而且, 变量只能存在于一个过程内, 因此它不能通过过程来传递值. 另一方面, 信号有多个值. 不论何时分配信号, vhdl仿真都会在某个仿真时段安排一个事件来更新信号的值. 在仿真时域里, 信号不会立即获得这个新的值. 而且信号可以存在于过程之外. 听起来好象有点复杂, 但大多数时候, 在硬件设计中可以只使用vhdl "信号". ）
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