TLC549的驱动代码
module TLC549 (input clk,
input reset,
input AD_DATA,
output AD_CS,
output AD_CLK,
output clk_display,
output reg readdata
);
// clk=50MHz , AD_CLK_r = 1MHz
regAD_CLK_r;
reg DCLK_DIV;
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
DCLK_DIV <= 1'b0;
AD_CLK_r <= 1'b0;
end
else if(DCLK_DIV < 6'd50) DCLK_DIV <= DCLK_DIV+1'b1;
else
begin
DCLK_DIV <= 0;
AD_CLK_r <= ~AD_CLK_r;
end
end
assign clk_display = AD_CLK_r;
reg COUNTER;
always @(posedge AD_CLK_r or negedge reset)
begin
if(!reset) COUNTER <= 1'b0;
else COUNTER <= COUNTER+1'b1;
end
assign AD_CS = (COUNTER <= 5'd9)? 1'b0 : 1'b1;
assign AD_CLK =(COUNTER >= 5'd2 && COUNTER <= 5'd9)? AD_CLK_r : 1'b0;
reg data_reg;
always @(negedge AD_CLK_r)
begin
if(COUNTER >= 5'd2 && COUNTER <= 5'd9)
begin
data_reg <= AD_DATA;
data_reg <= data_reg;
end
elsereaddata <= data_reg;
end
endmodule
4、数码管显示代码：
module display(
input clk,
input data,
input reset,
output reg seg,
output reg com );
reg cnt;
always@(posedge clk or negedge reset)
begin
if(!reset) cnt <= 12'd0;
else cnt <= cnt + 1'b1;
end
reg seg_reg;
always@(cnt or data)
begin
case(cnt)
2'b00 : begin com <= 4'b1110; seg_reg <= data%8'd10; end
2'b01 : begin com <= 4'b1101; seg_reg <= data%8'd100/8'd10;end
2'b10 : begin com <= 4'b1011; seg_reg <= data/8'd100; end
default : begin com <= 4'b1111;seg_reg <= 8'bzzzz_zzzz;end
endcase
end
always @(com or seg_reg)
begin
case(seg_reg)
4'h0:seg=8'hc0; //显示0
4'h1:seg=8'hf9; //显示1
4'h2:seg=8'ha4; //显示2
4'h3:seg=8'hb0; //显示3
4'h4:seg=8'h99; //显示4
4'h5:seg=8'h92; //显示5
4'h6:seg=8'h82; //显示6
4'h7:seg=8'hf8; //显示7
4'h8:seg=8'h80; //显示8
4'h9:seg=8'h90; //显示9
default: seg=8'hff;
endcase
end
endmodule TLC549的驱动代码 TLC549的驱动代码
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