帮助下
有这个图（见附件），用matlab里的simulink自动生成的verilog代码如下：//-------------------------------------------------------------
//
//Module: mm
//Simulink Path: mm
//Created: 2011-07-22 22:00:29
//Hierarchy Level: 0
//
//
//-------------------------------------------------------------
`timescale 1 ns / 1 ns
module mm
(
clk,
reset,
clk_enable,
In1,
ce_out,
Out1
);
input clk;
input reset;
input clk_enable;
input In1;// double
outputce_out;
output Out1;// double
wire enb;
reg In1_1;// double
reg Unit_Delay_out1;// double
assign enb = clk_enable;
assign ce_out = enb;
always @* In1_1 <= $bitstoreal(In1);
always @ (posedge clk or posedge reset)
begin: Unit_Delay_process
if (reset == 1'b1) begin
Unit_Delay_out1 <= 0.0000000000000000E+000;
end
else begin
if (enb == 1'b1) begin
Unit_Delay_out1 <= In1_1;
end
end
end // Unit_Delay_process
assign Out1 = $realtobits(Unit_Delay_out1);
endmodule// mm
但在编译时，它说：always @* In1_1 <= $bitstoreal(In1); assign Out1 = $realtobits(Unit_Delay_out1);这两句有错误，不支持。请问下怎样把它改正确呢？？？谢了
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