m序列verilog
module pn_7(clk, clr_n, pn_out);input clk; //时钟输入
input clr_n; //复位输入
output pn_out; //pn码输出
reg register; //7位移位寄存器
parameter sta_start = 7'B1000000; //初试状态，可自己定
assign pn_out = register;
always @(posedge clk)
begin
if (!clr_n) register <= sta_start;
else register <= {register+register,register};
end
endmodule m序列verilog m序列verilog
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