sboles算法实现
reg mix1,mix2,mix3;always @(posedge clk or negedge rst_n)
if(~rst_n)
mix1<=24'd0;
else if(sft_en)
mix1<={mix1,pre_sft};
always @(posedge clk or negedge rst_n)
if(~rst_n)
mix2<=24'd0;
else if(sft_en)
mix2<={mix2,cur_sft};
always @(posedge clk or negedge rst_n)
if(~rst_n)
mix3<=24'd0;
else if(sft_en)
mix3<={mix3,nex_sft};
//计算dx,dy
regsigneddx,dy;
wire p00,p01,p02,p10,p12,p20,p21,p22;
assign p02=mix1;
assign p01=mix1;
assign p00=mix1;
assign p12=mix2;
//assign p11=mix2;
assign p10=mix2;
assign p22=mix2;
assign p21=mix2;
assign p20=mix2;
always @(posedge clk or negedge rst_n)
if(~rst_n)
dx<=11'd0;
else if(sft_en)//
dx<=(-{3'b000,mix1}) + (+{3'b000,p02 }) +
(-{3'b000,(p10<<1)}) + (+{3'b000,(p12<<1) }) +
(-{3'b000,p20}) + (+{3'b000,p22 }) ;
always @(posedge clk or negedge rst_n)
if(~rst_n)
dy<=11'd0;
else if(sft_en)//
dy= (-{3'b000,p00}) + (-{3'b000,(p01<<1)}) + (-{3'b000,p02}) +
(+{3'b000,p20}) + (+{3'b000,(p21<<1)}) + (+{3'b000,p22}) ;
//计算d
reg d;
wire dx_abs,dy_abs;
assign dx_abs=dx?~dx+1'b1:dx;
assign dy_abs=dy?~dy+1'b1:dy;
always @(posedge clk or negedge rst_n)
if(~rst_n)
d<=11'd0;
else if(sft_en)//
d<=dx_abs+dy_abs; sboles算法实现 sboles算法实现
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