crc3
`timescale 1ns/1nsmodule crc3;
reg clk,rst_n;
initial begin
clk=0;
rst_n=0;
#53 rst_n=1;
end
always #2 clk=~clk;
reg data_fm;
reg cnt;
always @(posedge clk or negedge rst_n)
if(~rst_n)
cnt<=8'd0;
else
cnt<=cnt+1'b1;
always @(posedge clk or negedge rst_n)
if(~rst_n)
data_fm<={$random}%256;
else if(cnt==8'hFF)
data_fm<={$random}%256;
reg data;
reg en_crc;
always @(posedge clk or negedge rst_n)
if(~rst_n)begin
en_crc<=1'b0;
data<=1'b0;end
else case(cnt)
8'd2 :begin en_crc<=1'b1;data<=data_fm;end
8'd3 :begin en_crc<=1'b1;data<=data_fm;end
8'd4 :begin en_crc<=1'b1;data<=data_fm;end
8'd5 :begin en_crc<=1'b1;data<=data_fm;end
8'd6 :begin en_crc<=1'b1;data<=data_fm;end
8'd7 :begin en_crc<=1'b1;data<=data_fm;end
8'd8 :begin en_crc<=1'b1;data<=data_fm;end
8'd9 :begin en_crc<=1'b1;data<=data_fm;end
default:en_crc<=1'b0;
endcase
wire crc_tb;
reg num_tb;
always @(posedge clk or negedge rst_n)
if(~rst_n)
num_tb<=8'd0;
else if(cnt==8'hFF)
num_tb<=num_tb+1'b1;
integer fid;
initial fid=$fopen("CRC_DATA.DAT");
always @(posedge clk)
if(cnt==8'd11)
$fdisplay(fid,"SDATA=%0h \tDb=%0b \tDh=%0h \tDd=%0d",data_fm ,crc_tb,crc_tb,crc_tb);
always @(posedge clk)
if(num_tb>8'd99) begin
$fclose(fid);
$stop;
end
//**************CRC计算*****************************************************
parameter CRC_INIT=3'b101;
reg crc_current;
wire crc_next;//G(X)=1101
assign crc_tb=crc_current;
always @(posedge clk or negedge rst_n)
if(~rst_n)
crc_current<=CRC_INIT;
else if(en_crc)
crc_current<=crc_next;
else
crc_current<=CRC_INIT;
wire feedback;
assign feedback=data^crc_current;
assign crc_next=(feedback*1'b1)^1'b0;
assign crc_next=(feedback*1'b0)^crc_current;
assign crc_next=(feedback*1'b1)^crc_current;
endmodule
页:
[1]
