audio_QPSK_dem.v
`timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2021/12/28 16:56:28
// Design Name:
// Module Name: audio_QPSK_dem
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module audio_QPSK_dem(
input clk, //36MHz
input rst,
input data_in_I,
input data_in_Q,
input data_in_valid,
input count,
input rx_axis_tready, //1ms assert once.
output data_out,
output data_out_valid,
output axis_tkeep,
output axis_tlast
);
reg cnt16;
reg data_en;
reg data_en_dly1;
reg data_in_I_dly1;
// reg data_in_Q_dly1;
reg data_in_valid_dly1;
reg data_out_valid_temp;
reg data_out_temp_i;
// reg data_out_temp_q;
reg cnt16_dly1;
wire data_start;
wire parallel_data_ready;
reg data_shift;
reg data_out_temp;
reg valid_out_temp;
reg cnt32;
always @(posedge clk) begin
if (rst) begin
cnt16 <= 5'd0;
end
else if (data_in_valid && cnt16 == 5'd16) begin
cnt16 <= 5'd0;
end
else if (data_in_valid && count == 12'd127) begin
cnt16 <= 5'd1;
end
else if (data_in_valid && |cnt16) begin
cnt16 <= cnt16 + 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
data_en <= 1'b0;
end
else if (data_in_valid && count == 12'd127) begin
data_en <= 1'b1;
end
else if (data_in_valid && cnt16 == 5'd16) begin
data_en <= 1'b0;
end
end
always @(posedge clk) begin
data_in_I_dly1 <= data_in_I;
// data_in_Q_dly1 <= data_in_Q;
data_in_valid_dly1 <= data_in_valid;
end
always @(posedge clk) begin
if (rst) begin
data_out_temp_i <= 1'b0;
end
else if (data_in_valid_dly1 && data_en && ((data_in_I_dly1 == 1'b0 && data_in_I_dly1 > 15'd50) || (data_in_I_dly1 == 1'b1 && data_in_I_dly1 < 15'd32717))) begin
case ({data_in_I_dly1})
1'b0: begin
data_out_temp_i <= 1'b1;
end
default : begin
data_out_temp_i <= 1'b0;
end
endcase
end
else begin
data_out_temp_i <= 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
data_out_valid_temp <= 1'b0;
end
else if (data_en && data_in_valid_dly1) begin
data_out_valid_temp <= 1'b1;
end
else begin
data_out_valid_temp <= 1'b0;
end
end
always @(posedge clk) begin
data_en_dly1 <= data_en;
cnt16_dly1 <= cnt16;
end
assign data_start = (data_en && ~data_en_dly1) ? 1'b1 : 1'b0;
assign parallel_data_ready = (~data_en && data_en_dly1) ? 1'b1 : 1'b0;
always @(posedge clk) begin
if (rst) begin
data_shift <= 16'd0;
end
else if (data_start) begin
data_shift <= 16'd0;
end
else if (~data_en_dly1) begin
data_shift <= 16'd0;
end
else if (data_en_dly1 && data_out_valid_temp) begin
case (cnt16_dly1)
5'd1:data_shift <= {data_shift,data_out_temp_i};
5'd2:data_shift <= {data_shift,data_out_temp_i,data_shift};
5'd3:data_shift <= {data_shift,data_out_temp_i,data_shift};
5'd4:data_shift <= {data_shift,data_out_temp_i,data_shift};
5'd5:data_shift <= {data_shift,data_out_temp_i,data_shift};
5'd6:data_shift <= {data_shift,data_out_temp_i,data_shift};
5'd7:data_shift <= {data_shift,data_out_temp_i,data_shift};
5'd8:data_shift <= {data_shift,data_out_temp_i,data_shift};
5'd9:data_shift <= {data_shift,data_out_temp_i,data_shift};
5'd10: data_shift <= {data_shift,data_out_temp_i,data_shift};
5'd11: data_shift <= {data_shift,data_out_temp_i,data_shift};
5'd12: data_shift <= {data_shift,data_out_temp_i,data_shift};
5'd13: data_shift <= {data_shift,data_out_temp_i,data_shift};
5'd14: data_shift <= {data_shift,data_out_temp_i,data_shift};
5'd15: data_shift <= {data_shift,data_out_temp_i,data_shift};
5'd16: data_shift <= {data_out_temp_i,data_shift};
default : data_shift <= 16'd0;
endcase
end
end
always @(posedge clk) begin
if (rst) begin
data_out_temp <= 16'd0;
end
else if (data_en_dly1 && data_out_valid_temp&& (cnt16_dly1==5'd16)) //if (parallel_data_ready )begin//&& rx_axis_tready) begin
data_out_temp <= {data_out_temp_i,data_shift};
end
end
always @(posedge clk) begin
if(rst)
valid_out_temp<=1'b0;
elseif(parallel_data_ready)
valid_out_temp <= 1'b1;//parallel_data_ready && rx_axis_tready;
else if(rx_axis_tready)
valid_out_temp<=1'b0;
end
always @(posedge clk) begin
if (rst) begin
cnt32 <= 5'd0;
end
else if (valid_out_temp && rx_axis_tready) begin
cnt32 <= cnt32 + 1'b1;
end
end
assign axis_tlast = (cnt32 == 5'd31) ? 1'b1 : 1'b0;
// always @(posedge clk) begin
// if (rx_axis_tready) begin
// valid_out_temp <= parallel_data_ready;
// end
// else if (parallel_data_ready) begin
// valid_out_temp <= 1'b1;
// end
// end
assign data_out = data_out_temp;
assign data_out_valid = valid_out_temp;
assign axis_tkeep = 2'b11;
endmodule
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