axi_interface_slave.v
`timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/01/20 10:22:04
// Design Name:
// Module Name: axi_interface_slave
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module axi_interface_slave(
input clk,
input rst,
input axis_tdata,
output axis_tready,
input axis_tvalid,
input data_re,
output data_out_i,
output data_out_q
);
reg data_reg;
reg valid_reg;
reg cnt512;
reg data_shift_i;
reg data_shift_q;
reg axis_tvalid_dly1;
reg data_1bit_valid;
assign axis_tready = data_re;
always @(posedge clk) begin
if (rst) begin
data_reg <= 16'd0;
end
else if (axis_tvalid && axis_tready) begin
data_reg <= axis_tdata;
end
else begin
data_reg <= data_reg;
end
end
always @(posedge clk) begin
if(rst)
valid_reg<=1'b0;
else if( axis_tready && axis_tvalid)
valid_reg <=1'b1;
else
valid_reg<=1'b0;
end
//--------------------parallel to serial---------------------------
always @(posedge clk) begin
if (rst) begin
cnt512 <= 9'd0;
end
else if (valid_reg) begin
cnt512 <= 9'd0;
end
else if (cnt512 == 9'd511) begin
cnt512 <= cnt512;
end
else begin
cnt512 <= cnt512 + 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
data_shift_i <= 16'd0;
end
else if (valid_reg) begin
data_shift_i <= data_reg;
end
else if (cnt512 == 9'd511) begin
data_shift_i <= 16'd0;
end
else if (cnt512 == 5'd31) begin
data_shift_i <= {data_shift_i,data_shift_i}; // from low to high
end
end
always @(posedge clk) begin
if (rst) begin
data_shift_q <= 16'd0;
end
else if (valid_reg) begin
data_shift_q <= 16'd0;
end
else if (cnt512 == 9'd511) begin
data_shift_q <= 16'd0;
end
else if (cnt512 == 5'd31) begin
data_shift_q <= {data_shift_q,data_shift_q}; // from low to high
end
end
assign data_out_i = data_shift_i;
assign data_out_q = data_shift_q;
endmodule
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