VHDL报错：loop must terminate within 10,000 iteration？？？
LIBRARY IEEE;--库声明USE IEEE.STD_LOGIC_1164.ALL;--程序包说明
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Cycle_Use IS--实体描述
PORT
(
a,Clock : IN STD_LOGIC;
v:OUT STD_LOGIC
);
END Cycle_Use;
ARCHITECTURE Done OF Cycle_Use IS --结构体说明
SIGNALb :INTEGER RANGE 0 TO 10000000;
BEGIN
yyy : PROCESS(a)
BEGIN
b<=0;
IF a='1' THEN
LOOP
b<=b+1;
EXIT WHEN b>10;
END LOOP;
v<='1';
END IF;
END PROCESS yyy;
END Done;
--Error (10536): VHDL Loop Statement error at Cycle_Use.vhd(18): loop must terminate within 10,000 iterations
--Error: Can't elaborate top-level user hierarchy
请高手指点一下：EP1C6Q240C8,我用的LOOPEXIT WHEN 为什么报这样的错误
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