仿真信号生成问题
library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test_fadder is
end entity test_fadder;
architecture arc1 of test_fadder is
component f_adder
port(ain,bin: in std_logic;
cin: in std_logic;
sum,cout: out std_logic);
end component;
signal test_a,test_b,test_c: std_logic;
signal test_co,test_s: std_logic;
begin
u0:f_adder port map(ain=>test_a,bin=>test_b,cin=>test_c,
cout=>test_co,sum=>test_s);
process
begin
test_a<='0';
wait for 400 ns;
test_a<='1';
wait for 400 ns;
test_a<='0';
wait for 200 ns;
test_a<='1';
wait for 1000 ns;
test_a<='0';
wait ;
end process;
process
begin
test_b<='0';
wait for 500 ns;
test_b<='1';
wait for 800 ns;
test_b<='0';
wait ;
end process;
process
begin
test_c<='0';
wait for 400 ns;
test_c<='1';
wait for 700 ns;
test_c<='0';
wait for 400 ns;
test_c<='1';
wait for 600 ns;
test_c<='0';
wait;
end process;
end;
我是以程序直接产生的方法生成仿真输入信号的，为什么点击时序仿真的时候说没有输入信号？？顶层实体名为f_adder,请高手指教，， 神马东东... 用verilog编写个激励测试下，你那搞得很乱
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