仿真无输出 请教高手
module pulse_counter_task_logic(divide_clk,
reset_n,
pulse_pos_input,
pulse_neg_input,
pulse_result,
pre_pulse_pos_1,
pre_pulse_neg_1,
);
input divide_clk; //Input Clock to be divided
input reset_n; //Reset
input pulse_pos_input; //input pulse positive
input pulse_neg_input; //input pulse negative
output pulse_result; // output pulse counter
output pre_pulse_neg_1;
output pre_pulse_pos_1;
reg pulse_result_r; //output pulse counter register
reg pre_pulse_pos; //pulse counter temporary register
reg pre_pulse_neg;
//clock divide Process
always @(posedge divide_clk or negedge reset_n)
begin
if (~reset_n)
pulse_result_r <= 8'h0;
else if (divide_clk)
pulse_result_r <= pre_pulse_pos + pre_pulse_neg;
else
pulse_result_r <= pulse_result_r;
end
// pulse measure process
always @(negedge pulse_pos_input or posedge divide_clk or negedge reset_n)
begin
if((~reset_n) | divide_clk )
begin
pre_pulse_pos <= 8'h0; //clear the pre_pulse
end
else
begin
pre_pulse_pos <= pre_pulse_pos + 8'h1;
end
end
always @(negedge pulse_neg_input or posedge divide_clk or negedge reset_n)
begin
if((~reset_n) | divide_clk )
begin
pre_pulse_neg <= 8'h0; //clear the pre_pulse
end
else
begin
pre_pulse_neg <= pre_pulse_neg - 8'h1;
end
end
assign pulse_result = pulse_result_r;
//assign irq = divide_clk;
assign pre_pulse_pos_1 = pre_pulse_pos;
assign pre_pulse_neg_1 = pre_pulse_neg;
endmodule
用quartusII自带的仿真器仿真出来的pulse_result 为什么时钟无输出请教高手？ 看不懂。。。 666666666666666666666
页:
[1]
