请教有关verilog编写的计时模块的问题。
自己这段时间学习verilog，编写了一段计时模块的程序，但是编译一直有问题。程序如下：module clock(clks,RESET,scin,mcin,madd,hadd,sout,mout,hout);
input clks,RESET,madd,hadd;
output scin,mcin;
output sout,mout,hout;
reg scin,mcin;
regsout,mout,hout;
always @(posedge clks)
if(!RESET)sout<=0;
else
begin
if(sout==59)
begin
sout<=0;
scin<=0;
end
else
begin
sout<=sout+1;
scin<=0;
end
end
always @(posedge scin or posedge madd) （问题主要出在这里，如果敏感源只是posedge scin，编译就没有问题，加上posedge madd以后
编译就不能通过）
if(!RESET)mout<=0;
else
begin
if(mout==59)
begin
mout<=0;
mcin<=0;
end
else
begin
mout<=mout+1;
mcin<=0;
end
end
always @(posedge mcin or posedge hadd) （此处的问题同上面）
if(!RESET)hout<=0;
else
begin
if(hout==23) hout<=0;
else hout<=hout+1;
end
endmodule
引起出现问题的句子我在上面的程序中已经标注出来了，出现的问题为Error (10200): Verilog HDL Conditional Statement error at clock.v(25):
cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
请大家帮我解决一下这个问题，谢谢了！ 因为你这么写画不出电路 一个d触发器只有一个边沿触发信号 如果有两个 就要用选通电路选通一下 回复 2# jahero
朋友，能说的详细一些吗 module clock
(
clks,
reset,
scin,
mcin,
madd,
hadd,
sout,
mout,
hout
);
input clks;
input reset;
input madd;
input hadd;
output scin;
output mcin;
output sout;
output mout;
output hout;
reg scin;
reg mcin;
reg sout;
reg mout;
reg hout;
always @ (posedge clks or posedge reset)
begin
if (reset == 1'b1)
begin
sout <= 6'd0;
scin <= 1'b0;
end
else if (sout >= 6'd59)
begin
sout <= 6'd0;
scin <= 1'b1;
end
else
begin
sout <= sout + 6'd1;
scin <= 1'b0;
end
end
always @ (posedge clks or posedge reset)
begin
if (reset == 1'b1)
begin
mout <= 6'd0;
mcin <= 1'b0;
end
else if ((madd == 1'b1) || (scin == 1'b1))
begin
if (mout >= 6'd59)
begin
mout <= 6'd0;
mcin <= 1'b1;
end
else
begin
mout <= mout + 6'd1;
mcin <= 1'b0;
end
end
else ;
end
always @ (posedge clks or posedge reset)
begin
if (reset == 1'b1)
begin
hout <= 5'd0;
end
else if ((hadd == 1'b1) || ((scin == 1'b1) && (mcin == 1'b1)))
begin
if (hout >= 5'd23)
hout <= 5'd0;
else
hout <= hout + 5'd1;
end
else ;
end
endmodule
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