郁闷
程序功能不能实现，又找不出原因，郁闷，只能麻烦各位高手看看指点指点了程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key_test is
port(start_stop,reset,clk,en: in std_logic;
rst: out std_logic;
eno: out std_logic);
end key_test;
architecture behav of key_test is
signal station1:std_logic_vector(1 downto 0):="00";
signal station2:std_logic_vector(1 downto 0):="00";
signal sum_tmp:std_logic_vector(3 downto 0);
signal co_tmp:std_logic;
signal rst_tmp:std_logic:='1';
signal eno_tmp:std_logic:='0';
component cnt10_test
port(reset,en,clk:in std_logic;
sum: out std_logic_vector(3 downto 0);
co: out std_logic);
end component;
begin
u0:cnt10_test port map(reset,en,clk,sum_tmp,co_tmp);
process(reset,co_tmp) is
begin
if(reset='0') then
if(co_tmp'event and co_tmp='1') then
case station1 is
when "00"=>station1<="01";
when "01"=>station1<="10";
when "10"=>station1<="11";
when "11"=>station1<="11";
when others=>station1<="00";
end case;
end if;
else
station1<="00";
end if;
if(start_stop'event and start_stop='1') then
if(station2="11") then
rst_tmp<='0';
end if;
end if;
end process;
process(start_stop,co_tmp) is
begin
if(start_stop='1') then
if(co_tmp'event and co_tmp='1') then
case station2 is
when "00"=>station2<="01";
when "01"=>station2<="10";
when "10"=>station2<="11";
when "11"=>station2<="11";
when others=>station2<="00";
end case;
end if;
else
station2<="00";
end if;
if(start_stop'event and start_stop='0') then
if(station2="11") then
eno_tmp<=not eno_tmp;
end if;
end if;
end process;
eno<=eno_tmp;
rst<=rst_tmp;
end behav;
试图将按键去抖动后转变为控制信号，但是reset信号的转换不能实现，望高手不吝赐教 你把reset改成边沿触发试试 对了告我一声 不好意思，还是不对，还是谢谢你， 我想问问你是不是自带的仿真器与modelsim仿真的结果有差异 我感觉应该有差异，好像不能综合的语句在quartus里面仿不出来 建议你把case那块改一下
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