哪位牛人帮我看看我的VHDL程序哪里有问题？
library ieee;use ieee.std_logic_1164.all;
entity desplay is
port(
indate:in integer range 0 to 9;
inadd:in integer range 1 to 8;
outdate:out std_logic_vector(7 downto 0);
outadd:out std_logic_vector(7 downto 0));
end desplay;
architecture behave of desplay is
begin
U1: process(indate)
begin
case indate is
when 0 =>outdate<=x"c0";----0
when 1 =>outdate<=x"f9";----1
when 2 =>outdate<=x"a4";----2
when 3 =>outdate<=x"b0";----3
when 4 =>outdate<=x"99";----4
when 5 =>outdate<=x"92";----5
when 6 =>outdate<=x"82";----6
when 7 =>outdate<=x"f8";----7
when 8 =>outdate<=x"80";----8
when 9 =>outdate<=x"90";----9
when others =>outdate<=x"ff";
end case;
end process;
U2: process(inadd)
begin
case inadd is
when 1 =>outadd<="00000001";
when 2 =>outadd<="00000010";
when 3 =>outadd<="00000100";
when 4 =>outadd<="00001000";
when 5 =>outadd<="00010000";
when 6 =>outadd<="00100000";
when 7 =>outadd<="01000000";
when 8 =>outadd<="10000000";
when others =>outadd<="11111111";
end case;
end process;
end behave;
library ieee;
use ieee.std_logic_1164.all;
entity smg is
port(
outadd :out std_logic_vector(7 downto 0);
outdate:out std_logic_vector(7 downto 0)
);
end smg;
architecture art of smg is
component desplay
port(
indate:in integer range 0 to 9;
inadd:in integer range 1 to 8;
outdate:out std_logic_vector(7 downto 0);
outadd:out std_logic_vector(7 downto 0));
end component desplay;
begin
u1: desplay port map(2,5,outdate,outadd);
end art;
用Quartus仿真出得结果却是
这个程序只是一个简单的数码管显示的程序，只不过我想用元件例化做 将问题发到这里 http://www.fpgaw.com/thread-14188-1-1.html
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