jiangcaoyong 发表于 2011-12-9 23:09:02

请 高手编个电子钟程序,要带按键的,看看我的程序怎么去抖动

module clk(Clk0,Clk1,Change,Mkey,Hkey,SEG,DIG);
input      Clk0,Clk1,Change,Mkey,Hkey;//clk0为FPGA晶振频率，clk1为1hz时钟频率
output SEG,DIG;//数码管的段选和位选
reg    CNT_R0;
reg          F_OUT;
reg     HOUR,MIN,SEC;
wire         hclk,mclk;
reg          flag,mc,hc;
reg     SCAN_R;
reg     SEG_M ;
reg     SEG_DR;
reg     SEG,DIG;
always @(posedge Clk0)//分频
begin
   CNT_R0 <= CNT_R0 + 1'b1;

   if(CNT_R0 < 4096)
   begin
      F_OUT <= 1;
   end
   else
   begin
      F_OUT <= 0;
   end
end
always @(posedge F_OUT)
begin
   SCAN_R = SCAN_R + 1'b1;

   case(SCAN_R)
      3'h0 : begin DIG = 8'hFE; SEG_DR = SEG_M; end
      3'h1 : begin DIG = 8'hFD; SEG_DR = SEG_M; end
      3'h2 : begin DIG = 8'hFB; SEG_DR = SEG_M; end
      3'h3 : begin DIG = 8'hF7; SEG_DR = SEG_M; end
      3'h4 : begin DIG = 8'hEF; SEG_DR = SEG_M; end
      3'h5 : begin DIG = 8'hDF; SEG_DR = SEG_M; end
      3'h6 : begin DIG = 8'hBF; SEG_DR = SEG_M; end
      3'h7 : begin DIG = 8'h7F; SEG_DR = SEG_M; end
   endcase
end
always @(posedge Clk0)
begin
   case(SEG_DR)
      4'h0 : SEG <= 8'h3F;
      4'h1 : SEG <= 8'h06;
      4'h2 : SEG <= 8'h5B;
      4'h3 : SEG <= 8'h4F;
      4'h4 : SEG <= 8'h66;
      4'h5 : SEG <= 8'h6D;
      4'h6 : SEG <= 8'h7D;
      4'h7 : SEG <= 8'h07;
      4'h8 : SEG <= 8'h7F;
      4'h9 : SEG <= 8'h6F;
      4'hA : SEG <= 8'h40;
   default : SEG <= 4'h00;
   endcase
end
always @(posedge Change)//选择手动调时还是正常计时
begin
if(flag==0)
flag<=1;
else
flag<=0;
end
always @(posedge Clk1)
begin
   if(SEC==8'b01011001)begin SEC<=0; if(flag==0)mc<=1;else mc<=mc;end
   else begin
   if(SEC==4'b1001)
   begin SEC<=0;SEC<=SEC+1'b1;if(flag==0)mc<=0;else mc<=mc;end
   else
   begin
       SEC<=SEC+1'b1;if(flag==0)mc<=0;else mc<=mc; end
   end
end
assign mclk=(flag==0)?(!flag&mc):(!mc&Mkey)|(mc&!Mkey);
always @(posedge mclk)
begin
   if(MIN==8'b01011001)begin MIN<=0; if(flag==0)hc<=1;else hc<=hc;end
   else begin
   if(MIN==4'b1001)
   begin
MIN<=0;MIN<=MIN+1'b1;if(flag==0)hc<=0;else hc<=hc;end
   else
   begin
       MIN<=MIN+1'b1;if(flag==0)hc<=0;else hc<=hc; end
   end
end
assign hclk=(flag==0)?(!flag&hc):(!hc&Hkey)|(hc&!Hkey);
always @(posedge hclk)
begin
   if(HOUR==8'h00100011) HOUR<=0;
   elsebegin
if(HOUR==4'b1001)begin HOUR<=0;HOUR<=HOUR+1'b1;end
else
       HOUR<=HOUR+1'b1;
end
end
always @(posedge Clk0)
begin
   SEG_M = SEC;
   SEG_M = SEC;
   SEG_M = 4'hA;
   SEG_M = MIN;
   SEG_M = MIN;
   SEG_M = 4'hA;
   SEG_M = HOUR;
   SEG_M = HOUR;
end
endmodule

I2C 发表于 2011-12-12 06:41:56

把问题发到这里 http://www.fpgaw.com/thread-14188-1-1.html
页: [1]
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