跪求高手指点
------------------------------------------------------------------------------------ Company:
-- Engineer:
--
-- Create Date: 16:09:01 01/04/2012
-- Design Name:
-- Module Name: Uart_mysilf - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Uart_mysilf is
port(clk:in std_logic;
rx :in std_logic;
-- tx_flage :in std_logic;
rx_flage :out std_logic;
tx : out std_logic
-- clkout : out std_logic
);
end Uart_mysilf;
architecture Behavioral of Uart_mysilf is
signal cnt : std_logic_vector(15 downto 0) :="0000000000000000";
signal cnt1 : std_logic_vector(3 downto 0) :="0000";
signal cnt2 : std_logic_vector(3 downto 0) :="0000";
signal tx_buffer : std_logic_vector(7 downto 0) :="00000000";
signal rx_buffer : std_logic_vector(7 downto 0) :="00000000";
signal bclk : std_logic :='0';
--signal rx_flage: std_logic:='0' ;
signal tx_flage : std_logic:='0' ;
signal send : std_logic:='0' ;
begin
process(clk)
begin
cnt<=cnt+"0000000000000001";
if(cnt="00000000001010000101")then
bclk<='0';
elsif(cnt="000000000010100001010")then
bclk<='1';
cnt<="0000000000000000";
end if;
end process;
process(bclk)
begin
if(bclk='1') then
if(rx='0')then
cnt2<=cnt2+"0001";
end if;
--end if;
case cnt2 is
when "0001" =>
rx_buffer(0)<=rx;
cnt2<=cnt2+"0001";
when "0010" =>
rx_buffer(1)<=rx;
cnt2<=cnt2+"0001";
when "0011" =>
rx_buffer(2)<=rx;
cnt2<=cnt2+"0001";
when "0100" =>
rx_buffer(3)<=rx;
cnt2<=cnt2+"0001";
when "0101" =>
rx_buffer(4)<=rx;
cnt2<=cnt2+"0001";
when "0110" =>
rx_buffer(5)<=rx;
cnt2<=cnt2+"0001";
when "0111" =>
rx_buffer(6)<=rx;
cnt2<=cnt2+"0001";
when "1000" =>
rx_buffer(7)<=rx;
cnt2<=cnt2+"0001";
when "1001" =>
-- tx_buffer<=rx_buffer;
tx_flage<='1';
rx_flage<='1';
when others =>
-- cnt1<=cnt1;
end case;
if(cnt2="1001") then
--- tx_flage<='1';
cnt2<="0000";
end if;
end if;
end process;
process(bclk)
begin
tx_buffer<="01011010";
if(bclk='1') then
if(tx_flage='1') then
cnt1<=cnt1+"0001";
tx_flage<='0';
end if;
case cnt1 is
when "0001" =>
tx<='0';
cnt1<=cnt1+"0001";
when "0010" =>
tx<=tx_buffer(0);
cnt1<=cnt1+"0001";
when "0011" =>
tx<=tx_buffer(1);
cnt1<=cnt1+"0001";
when "0100" =>
tx<=tx_buffer(2);
cnt1<=cnt1+"0001";
when "0101" =>
tx<=tx_buffer(3);
cnt1<=cnt1+"0001";
when "0110" =>
tx<=tx_buffer(4);
cnt1<=cnt1+"0001";
when "0111" =>
tx<=tx_buffer(5);
cnt1<=cnt1+"0001";
when "1000" =>
tx<=tx_buffer(6);
cnt1<=cnt1+"0001";
when "1001" =>
tx<=tx_buffer(7);
cnt1<=cnt1+"0001";
when "1010" =>
tx<='1';
cnt1<="0000";
-- tx_flage<='0';
-- cnt1<="0000";
when others =>
-- cnt1<=cnt1;
end case;
end if;
end process;
end Behavioral;
在编译的时候出现错误啊
ERROR:Xst:528 - Multi-source in Unit <Uart_mysilf> on signal <tx_flage>
Sources are:
Output signal of LDE instance <tx_flage/0>
Signal <tx_flage> in Unit <Uart_mysilf> is assigned to GND
CPU : 2.70 / 2.83 s | Elapsed : 3.00 / 3.00 s
跪求高手指点 跪求高手帮我找找原因啊 高手在哪啊
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