哪位做过基于FPGA函数信号发生器（频率和相位可调，VHDL语言编写的）的前辈
哪位做过基于FPGA函数信号发生器（频率和相位可调，VHDL语言编写的）的前辈。能不能借鉴下啊，我是刚学FPGA方面，不太懂 这个使用DDS技术很容易做到。我用VERILOG写过这个东西，如有需要可与我联系，下面给你一个参考代码。sine.v文件
module sine(
inputclk,
inputphase,
inputnRst,
output data
);
reg addr;
always@(posedge clk or negedge nRst)begin
if(!nRst)begin
addr <= phase;
end
else begin
addr <= addr +1'b1;
end
end
sineData GenerateSineDataByAddr(
.clock(clk),
.address(addr),
.q(data)
);
//SineData.v文件
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sineData.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors.Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sineData (
address,
clock,
q);
input address;
input clock;
output q;
wire sub_wire0;
wire q = sub_wire0;
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "sine.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "sine.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "sine.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL q
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL sineData.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sineData.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sineData.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sineData.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sineData_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sineData_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sineData_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sineData_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
//sine.mif文件
DEPTH = 256;
WIDTH = 12;
ADDRESS_RADIX = HEX;
DATA_RADIX = DEC;
CONTENT
BEGIN
0000 :2048;
0001 :2098;
0002 :2148;
0003 :2198;
0004 :2248;
0005 :2298;
0006 :2348;
0007 :2398;
0008 :2447;
0009 :2496;
000A :2545;
000B :2594;
000C :2642;
000D :2690;
000E :2737;
000F :2784;
0010 :2831;
0011 :2877;
0012 :2923;
0013 :2968;
0014 :3013;
0015 :3057;
0016 :3100;
0017 :3143;
0018 :3185;
0019 :3226;
001A :3267;
001B :3307;
001C :3346;
001D :3385;
001E :3423;
001F :3459;
0020 :3495;
0021 :3530;
0022 :3565;
0023 :3598;
0024 :3630;
0025 :3662;
0026 :3692;
0027 :3722;
0028 :3750;
0029 :3777;
002A :3804;
002B :3829;
002C :3853;
002D :3876;
002E :3898;
002F :3919;
0030 :3939;
0031 :3958;
0032 :3975;
0033 :3992;
0034 :4007;
0035 :4021;
0036 :4034;
0037 :4045;
0038 :4056;
0039 :4065;
003A :4073;
003B :4080;
003C :4085;
003D :4089;
003E :4093;
003F :4094;
0040 :4095;
0041 :4094;
0042 :4093;
0043 :4089;
0044 :4085;
0045 :4080;
0046 :4073;
0047 :4065;
0048 :4056;
0049 :4045;
004A :4034;
004B :4021;
004C :4007;
004D :3992;
004E :3975;
004F :3958;
0050 :3939;
0051 :3919;
0052 :3898;
0053 :3876;
0054 :3853;
0055 :3829;
0056 :3804;
0057 :3777;
0058 :3750;
0059 :3722;
005A :3692;
005B :3662;
005C :3630;
005D :3598;
005E :3565;
005F :3530;
0060 :3495;
0061 :3459;
0062 :3423;
0063 :3385;
0064 :3346;
0065 :3307;
0066 :3267;
0067 :3226;
0068 :3185;
0069 :3143;
006A :3100;
006B :3057;
006C :3013;
006D :2968;
006E :2923;
006F :2877;
0070 :2831;
0071 :2784;
0072 :2737;
0073 :2690;
0074 :2642;
0075 :2594;
0076 :2545;
0077 :2496;
0078 :2447;
0079 :2398;
007A :2348;
007B :2298;
007C :2248;
007D :2198;
007E :2148;
007F :2098;
0080 :2047;
0081 :1997;
0082 :1947;
0083 :1897;
0084 :1847;
0085 :1797;
0086 :1747;
0087 :1697;
0088 :1648;
0089 :1599;
008A :1550;
008B :1501;
008C :1453;
008D :1405;
008E :1358;
008F :1311;
0090 :1264;
0091 :1218;
0092 :1172;
0093 :1127;
0094 :1082;
0095 :1038;
0096 : 995;
0097 : 952;
0098 : 910;
0099 : 869;
009A : 828;
009B : 788;
009C : 749;
009D : 710;
009E : 672;
009F : 636;
00A0 : 600;
00A1 : 565;
00A2 : 530;
00A3 : 497;
00A4 : 465;
00A5 : 433;
00A6 : 403;
00A7 : 373;
00A8 : 345;
00A9 : 318;
00AA : 291;
00AB : 266;
00AC : 242;
00AD : 219;
00AE : 197;
00AF : 176;
00B0 : 156;
00B1 : 137;
00B2 : 120;
00B3 : 103;
00B4 : 88;
00B5 : 74;
00B6 : 61;
00B7 : 50;
00B8 : 39;
00B9 : 30;
00BA : 22;
00BB : 15;
00BC : 10;
00BD : 6;
00BE : 2;
00BF : 1;
00C0 : 0;
00C1 : 1;
00C2 : 2;
00C3 : 6;
00C4 : 10;
00C5 : 15;
00C6 : 22;
00C7 : 30;
00C8 : 39;
00C9 : 50;
00CA : 61;
00CB : 74;
00CC : 88;
00CD : 103;
00CE : 120;
00CF : 137;
00D0 : 156;
00D1 : 176;
00D2 : 197;
00D3 : 219;
00D4 : 242;
00D5 : 266;
00D6 : 291;
00D7 : 318;
00D8 : 345;
00D9 : 373;
00DA : 403;
00DB : 433;
00DC : 465;
00DD : 497;
00DE : 530;
00DF : 565;
00E0 : 600;
00E1 : 636;
00E2 : 672;
00E3 : 710;
00E4 : 749;
00E5 : 788;
00E6 : 828;
00E7 : 869;
00E8 : 910;
00E9 : 952;
00EA : 995;
00EB :1038;
00EC :1082;
00ED :1127;
00EE :1172;
00EF :1218;
00F0 :1264;
00F1 :1311;
00F2 :1358;
00F3 :1405;
00F4 :1453;
00F5 :1501;
00F6 :1550;
00F7 :1599;
00F8 :1648;
00F9 :1697;
00FA :1747;
00FB :1797;
00FC :1847;
00FD :1897;
00FE :1947;
00FF :1997;
END ;
endmodule
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