请大家帮我看看这个testbench的程序，谢谢大家
我在quatus里仿真就没问题，而在Modelsim仿真不出来（编译通过），帮我看看我的testbench哪写错了我的testbench代码：
`timescale 1ns/1ns
module shideng_tb ( );
parameter period=20;
// input port
reg clk;
reg rst_b;
//output port
wire LED_1;
wire LED_2;
wire LED_3;
wire LED_4;
// DUT:device under test
shideng dut(
.clk(clk),
.rst_b(rst_b),
.LED_1(LED_1),
.LED_2(LED_2),
.LED_3(LED_3),
.LED_4(LED_4)
);
// clock
initial
begin
clk=0;
forever
#(period/2) clk=~clk;
end
//reset
initial
begin
reset_test(50);
end
// task
task reset_test;
input reset_time; //reset time
begin
rst_b=0;
#(reset_time) rst_b=1;
end
endtask
endmodule
源程序代码：
module shideng (LED_1, LED_2, LED_3, LED_4, clk, rst_b);
input clk, rst_b;
output LED_1, LED_2, LED_3, LED_4;
reg LED_1, LED_2, LED_3, LED_4;
reg clk_2s, clk_1s, clk_half, clk_qtr;
reg DATA_NUM1, DATA_NUM2, DATA_NUM3, DATA_NUM4;
always@(negedge rst_b or posedge clk)
begin
if(!rst_b)
DATA_NUM1<=0;
else if(DATA_NUM1==28'h8)
begin
DATA_NUM1<=0;
clk_2s<=~clk_2s;
end
else
begin
clk_2s<=clk_2s;
DATA_NUM1<=DATA_NUM1+1;
end
end
always@(negedge rst_b or posedge clk)
begin
if(!rst_b)
DATA_NUM2<=0;
else if(DATA_NUM2==28'h4)
begin
DATA_NUM2<=0;
clk_1s<=~clk_1s;
end
else
begin
clk_1s<=clk_1s;
DATA_NUM2<=DATA_NUM2+1;
end
end
always@(negedge rst_b or posedge clk)
begin
if(!rst_b)
DATA_NUM3<=0;
else if(DATA_NUM3==28'h2)
begin
DATA_NUM3<=0;
clk_half<=~clk_half;
end
else
begin
clk_half<=clk_half;
DATA_NUM3<=DATA_NUM3+1;
end
end
always@(negedge rst_b or posedge clk)
begin
if(!rst_b)
DATA_NUM4<=0;
else if(DATA_NUM4==28'h1)
begin
DATA_NUM4<=0;
clk_qtr<=~clk_qtr;
end
else
begin
clk_qtr<=clk_qtr;
DATA_NUM4<=DATA_NUM4+1;
end
end
always@(posedge clk_2s or negedge rst_b)
begin
if(!rst_b)
LED_1<=1;
else
LED_1<=~LED_1;
end
always@(posedge clk_1s or negedge rst_b)
begin
if(!rst_b)
LED_2<=1;
else
LED_2<=~LED_2;
end
always@(posedge clk_half or negedge rst_b)
begin
if(!rst_b)
LED_3<=1;
else
LED_3<=~LED_3;
end
always@(posedge clk_qtr or negedge rst_b)
begin
if(!rst_b)
LED_4<=1;
else
LED_4<=~LED_4;
end
endmodule
Quatus波形正确
modelsim输出全为1 自己顶一下，大家帮帮忙 是不是在modelsim中没有加载testbench？还是没有编译生成库？看你的程序应该没问题，再说Quartus ii可以出现波形，应该就是加载的问题了 是不是在modelsim中没有加载testbench？还是没有编译生成库？看你的程序应该没问题，再说Quartus ii可以出现波形，应该就是加载的问题了 是不是在modelsim中没有加载testbench？还是没有编译生成库？看你的程序应该没问题，再说Quartus ii可以出现波形，应该就是加载的问题了 是不是在modelsim中没有加载testbench？还是没有编译生成库？看你的程序应该没问题，再说Quartus ii可以出现波形，应该就是加载的问题了
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