状态机举例-Verilog HDL 代码
本帖最后由 fpgaw 于 2010-11-18 16:00 编辑状态机举例-Verilog HDL 程序举例
一个同步状态机
Verilog HDL: Synchronous State Machine
This is a Verilog example that shows the implementation of a state machine.
The first CASE statement defines the outputs that are dependent on the value of the state machine variable state.
The second CASE statement defines the transitions of state machine and the conditions that control them.
statem.v
module statem(clk, in, reset, out);
input clk, in, reset;
output out;
reg out;
reg state;
parameter zero=0, one=1, two=2, three=3;
always @(state)
begin
case (state)
zero:
out = 4'b0000;
one:
out = 4'b0001;
two:
out = 4'b0010;
three:
out = 4'b0100;
default:
out = 4'b0000;
endcase
end
always @(posedge clk or posedge reset)
begin
if (reset)
state = zero;
else
case (state)
zero:
state = one;
one:
if (in)
state = zero;
else
state = two;
two:
state = three;
three:
state = zero;
endcase
end
endmodule 状态机是很有用的一个东西
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