简单的Verilog HDL 程序。交通灯
自己写的一个交通灯的程序，一个十字路口，red_o,blue_o,green_o, 表示主交通道上的红，绿，黄灯，1表示亮
red_1_o,blue_1_o,green_1_0,表示人行道上的红，绿，黄灯
用Modelsim仿真结果不好，请各位帮帮我。
module trafficlight (clk,rst,c,red_o,blue_o,green_o,
red_1_o,blue_1_o,green_1_o);
input clk,rst,c; //c=1,表示有人过路
output red_o,blue_o,green_o,red_1_o,blue_1_o,green_1_o;
reg red_o,blue_o,green_o,red_1_o,blue_1_o,green_1_o;
reg cnt;
`define DA_LIGHT {red_o,blue_o,green_o}
`define XIAO_LIGHT {red_1_o,blue_1_o,green_1_o}
parameter b_g_n=20; //绿灯转黄灯的计数时间
parameter g_r_n=10; //黄灯装红灯的计数时间
parameter stt=30; //小马路上的行车时间
//公路上的红绿灯
always @ (posedge clk or negedge rst)begin
if(!rst)begin
`DA_LIGHT<=3'b010;
`XIAO_LIGHT<=3'b100;
end
else begin
case ({`DA_LIGHT,`XIAO_LIGHT})
6'b010100:
begin
if (c==1) begin
delay (b_g_n,cnt);
wait (cnt)
`DA_LIGHT<=3'b001;
`XIAO_LIGHT<=3'b100;
end
end
6'b001100:
begin
delay (g_r_n,cnt);
wait (cnt);
`DA_LIGHT<=3'b100;
`XIAO_LIGHT<=3'b010;
end
6'b100010:
begin
delay(stt,cnt);
wait(cnt);
`DA_LIGHT<=3'b100;
`XIAO_LIGHT<=3'b001;
end
6'b100001:
begin
delay(g_r_n,cnt);
wait(cnt);
`DA_LIGHT<=3'b010;
`XIAO_LIGHT<=3'b100;
end
default:
begin
`DA_LIGHT<=3'b010;
`XIAO_LIGHT<=3'b100;
end
endcase
end
end
//延时的程序
task delay;
input tics;
output cnt;
reg cnt;
begin
repeat (tics)
@(posedge clk);
cnt<=1;
end
endtask
endmodule 用状态机设计的交通灯控制器 verilog hdl
http://www.fpgaw.com/viewthread.php?tid=2186&highlight=%BD%BB%CD%A8%B5%C6 交通灯源码
交通灯
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TrafficLight IS
PORT (Clk : IN STD_LOGIC;
S,Reset : IN STD_LOGIC;
LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
Mg,My,Mr,Cg,Cy,Cr : OUT STD_LOGIC );
END TrafficLight ;
ARCHITECTURE rtl OF TrafficLight IS
TYPE TrafficState IS (mgcr, mycr, mrcg, mrcy);
SIGNAL State: TrafficState ;
SIGNAL DataOut : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL Count: STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL SetCount : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL Clrn : STD_LOGIC ;
SIGNAL LEDB : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
Counter : PROCESS(clk)
BEGIN
IF Reset = '1' OR (Clrn = '1' AND NOT(Count = "000000")) THEN Count <= "000000";
ELSIF clk'EVENT AND clk = '1' THEN
IF NOT(Count = "111011" AND State = mgcr) THEN Count <= Count + 1;END IF;
END IF;
END PROCESS Counter;
StateTransition : PROCESS(clk)
BEGIN
IF Reset = '1' THEN State <= mgcr;Clrn <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
CASE State IS
WHEN mgcr => IF Count >= "111011" AND S = '1' THEN State <= mycr;Clrn <= '1';
ELSE Clrn <= '0';
END IF;
WHEN mycr => IF Count >= "000011" THEN State <= mrcg;Clrn <= '1';
ELSE Clrn <= '0';
END IF;
WHEN mrcg => IF Count >= "010011" OR S = '0' THEN State <= mrcy;Clrn <= '1';
ELSE Clrn <= '0';
END IF;
WHEN mrcy => IF Count >= "000011" THEN State <= mgcr;Clrn <= '1';
ELSE Clrn <= '0';
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS StateTransition;
CountDown : PROCESS(CLK)
BEGIN
IF LEDB > 59 THEN LED <= LEDB + 36;
ELSIF LEDB > 49 THEN LED <= LEDB + 30;
ELSIF LEDB > 39 THEN LED <= LEDB + 24;
ELSIF LEDB > 29 THEN LED <= LEDB + 18;
ELSIF LEDB > 19 THEN LED <= LEDB + 12;
ELSIF LEDB > 9 THEN LED <= LEDB + 6;
ELSE LED <= LEDB;
END IF;
END PROCESS CountDown;
Output : BLOCK
BEGIN
WITH State SELECT
DataOut <= "100001" WHEN mgcr,
"010001" WHEN mycr,
"001100" WHEN mrcg,
"001010" WHEN mrcy;
WITH State SELECT
SetCount <= "111100" WHEN mgcr,
"000100" WHEN mycr,
"010100" WHEN mrcg,
"000100" WHEN mrcy;
Mg <= DataOut(5);My <= DataOut(4);Mr <= DataOut(3);
Cg <= DataOut(2);Cy <= DataOut(1);Cr <= DataOut(0);
LEDB <= SetCount - ("00" & Count);
END BLOCK Output;
END ARCHITECTURE rtl; 交通灯控制器方案下载
http://www.fpgaw.com/viewthread.php?tid=219&highlight=%BD%BB%CD%A8%B5%C6 交通灯好多地方都有源程序啊 好的啊，谢谢啦！ 回复 3# IPO
同一个程序到处发，哎…… hao 。顶起》》》》》》》 看别人的代码 真的是很痛苦
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