qq87622 发表于 2010-6-3 13:35:43

求FPGA的描述性语言

下面是一些程序谁能告诉我关键的语句意思!!
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fenpinqi IS
PORT ( clk : In STD_LOGIC;
       clk_scan : OUT STD_LOGIC);
      END fenpinqi;
ARCHITECTURE rtl OF fenpinqi IS
SIGNAL cnt:INTEGER RANGE 0 TO 40000;
BEGIN
PROCESS(clk)
BEGIN
IF clk'event and clk='1' THEN
IF cnt=cnt'high THEN
   cnt<=0;
   ELSE
cnt<=cnt+1;
END IF;
END IF;
END PROCESS;
PROCESS(cnt,clk)
BEGIN
IF clk'event and clk='1' THEN
   IF cnt>= cnt'high/2 THEN
clk_scan<='1';
ELSE
   clk_scan<='0';
END IF;
END IF;
END PROCESS;
END rtl;

Sunlife 发表于 2015-5-20 10:22:36


坐等。。。VHDL 没学过
页: [1]
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