sram的verilog程序
timescale 1ns / 1ps////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: sram_test
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sram_test( rst ,
clkin ,
sram_ab ,
sram_db ,
sram_wr ,
sram_rd ,
sram_cs ,
sram_be ,
error,
task_start , //Start Testing ---LED1
task_finish,//TestingFinish---LED2
flash_ce,
flash_oe,
flash_we
);
input rst ;
input clkin ;
output sram_ab ;
output sram_be ;
inout sram_db ;
output sram_wr ;
output sram_rd ;
output sram_cs ;
output error;
output task_start ;
output task_finish;
output flash_ce,flash_oe,flash_we;
//ports
wire rst ;
wire clkin ;
reg sram_ab ;
wire sram_db ;
reg sram_wr ;
reg sram_rd ;
reg task_start ;
reg task_finish;
wire flash_ce=1;
wire flash_oe=1;
wire flash_we=1;
reg clk_2;
wire clk;
reg STATE,NEXT;
reg error ;
reg sram_db_reg;
reg count ;
//parameters
parameter IDLE = 3'D0,
WRITE_1= 3'D1,
WRITE_2= 3'D2,
READ_1 = 3'D3,
READ_2 = 3'D4;
assignsram_cs = 1'b0;
assignsram_be = 2'd0;
assignsram_db = sram_rd ? sram_db_reg:'hz;
reg clk_count;
always @(posedge clkin or negedge rst)
if(!rst)
begin
clk_count<=2'd0;
end
else
begin
clk_count<=clk_count+1'b1;
end
assign clk = clk_count;
//state machine
always @ (STATE or sram_ab or error or task_start)
begin
case(STATE)
IDLE : if(task_start)
NEXT = WRITE_1;
else
NEXT = IDLE ;
WRITE_1 : NEXT = WRITE_2;
WRITE_2 : if( sram_ab >= 18'h3ffff)
NEXT = READ_1;
else
NEXT = WRITE_1;
READ_1: NEXT = READ_2;
READ_2: if(sram_ab >= 18'h3ffff)//error ||
NEXT = IDLE;
else
NEXT = READ_1;
default : NEXT = IDLE ;
endcase
end
//registe the state
always @ (posedge clk or negedge rst)
if(!rst)
STATE <= IDLE;
else
STATE <= NEXT;
always @ (posedge clk or negedge rst)
if(!rst)
begin
sram_ab <=18'h3ffff;
sram_db_reg<=16'h1fff;
sram_wr <=1'b1;
sram_rd <=1'b1;
end
else
case(STATE)
IDLE : begin
sram_rd <= 1;
sram_wr <= 1;
end
WRITE_1 : begin
sram_ab <= sram_ab+1;
sram_db_reg <= sram_db_reg+1;
sram_wr <= 1'b0;
sram_rd <= 1'b1;
end
WRITE_2 : begin
sram_wr<= 1'b1;
sram_rd<= 1'b1;
end
READ_1: begin
sram_ab <= sram_ab+1;
sram_wr <= 1'b1;
sram_rd <= 1'b0;
sram_db_reg <= 'h1fff;
end
endcase
always @ (posedge clk or negedge rst)
if(!rst)
begin
error <= 1'b0;
task_start <= 1'b1;
task_finish<= 1'b0;
count <= 16'h1fff;
end
else
case(STATE)
WRITE_1 : //if( sram_ab < 'd1024 )
begin
task_start <= 1'b1;
count <= 16'h1fff;
end
READ_1: begin
count<=count+1;
end
READ_2: begin
if( sram_db != count)
error <= 1'b1;
else
begin
error <= 1'b0;
if(sram_ab >= 18'h3ffff)
begin
task_finish <= 1'b1;
//task_start<= 1'b1;
end
end
end
endcase
endmodule
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