CHANG 发表于 2010-6-26 01:48:57

one-hot状态机两种编码方式综合成果的比较

本帖最后由 fpgaw 于 2010-11-19 06:41 编辑

1.非index编码方式
`timescale 1ns/10ps
module test_sm(
   clk,
   rst_n,   
   state_out
   );
   
input    clk;
input    rst_n;
output state_out;
wire state_out;
parameter    U_DLY = 1;               
   
parameter    STATE0 = 6'b000001,
       STATE1 = 6'b000010,
       STATE2 = 6'b000100,   
       STATE3 = 6'b001000,
       STATE4 = 6'b010000,
       STATE5 = 6'b100000;
reg     current_state;
reg     next_state;   
assignstate_out = current_state;
//------------------------------state machine---------------------------
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
current_state <= STATE0;
else
current_state <= #U_DLY next_state;   
end

always @(current_state)
begin
case (current_state) //synopsys parallel case
STATE0:
    next_state = STATE1;

STATE1:
    next_state = STATE2;
      
STATE2:
    next_state = STATE3;         
      
STATE3:
    next_state = STATE4;

STATE4:
    next_state = STATE5;
STATE5:
    next_state = STATE0;
default:
    next_state = STATE0;            
endcase   
end
endmodule
2.index编码方式
`timescale 1ns/10ps
module test_sm(
   clk,
   rst_n,   
   state_out
   );
   
input    clk;
input    rst_n;
output state_out;
wire state_out;
parameter    U_DLY = 1;               
   
parameter    STATE0 = 0,
       STATE1 = 1,
       STATE2 = 2,   
       STATE3 = 3,
       STATE4 = 4,
       STATE5 = 5;
reg     current_state;
reg     next_state;   
assignstate_out = current_state;
//------------------------------state machine---------------------------
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
current_state <= 6'b1;//because the coding of IDLE is 000001
else
current_state <= #U_DLY next_state;   
end

always @(current_state)
begin
next_state = 6'b0;
case (1'b1) //synopsys parallel case
current_state:
    next_state = 1'b1;

current_state:
    next_state = 1'b1;
      
current_state:
    next_state = 1'b1;         
      
current_state:
    next_state = 1'b1;

current_state:
    next_state = 1'b1;
current_state:
    next_state = 1'b1;            
endcase   
end
endmodule
综合工具synplify、quartus4.1,器件用cyclone EP1C4-I7,没有加任务约束。
用synplify的流程为:先在synplify下综合,再导入quartus4.1布局布线。
不用synplify的流程为:直接在quartus4.1下综合。
结果:
a.非index编码:
       资源占用 频率
synplify    6个LE 320M
quartus   10个LE320M
b.index编码
       资源占用 频率
synplify    6个LE 320M
quartus   7个LE 320M
注:synplify将它综合成移位寄存器了,不过在另外一个用index编码的复杂的状态机中,
它是将其综合成状态机了。synplify可以认index编码的状态机,而quartus似乎不行(通过
rtl viewer来看)

CHANG 发表于 2010-6-26 02:37:30

综合出来的频率相同的原因可能是这状态机较为简单,体现不出差异
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