我的状态机是怎么回事??
本帖最后由 fpgaw 于 2010-11-19 06:45 编辑大家看看我的程序和仿真的时序,前面的状态机没定义,怎么改?
ENTITY sample_addr_generator IS
PORT
(
clk : in std_logic; -- 时钟
le : in std_logic; --与采样 计数器连接
rst: in std_logic; --复位
rang: in STD_LOGIC_VECTOR(9 downto 0); --integer range 0 to 1023; --计数范围
addr : out STD_LOGIC_VECTOR(9 downto 0); --integer range 0 to 1023; --地址，连到采样缓存的写入地址端
wr : out std_logic;
stat : out std_logic --工作状态,0为可生成地址,1为发生地址已到计数范围,停止工作
);
END sample_addr_generator;
ARCHITECTURE a OF sample_addr_generator IS
TYPE STATE_TYPE IS (ST_RST, ST_IDEL,ST_INIT0, ST_INIT1, ST_INIT2, ST_INIT3, ST_LE0, ST_WR, ST_WAIT_LE0 );
SIGNAL state : STATE_TYPE := ST_IDEL;
SIGNAL cqi : STD_LOGIC_VECTOR(9 downto 0) := "0000000000"; --INTEGER RANGE 0 TO 1023 := 0;
BEGIN
PROCESS (clk, rst, le, rang)
BEGIN
-- 复位
IF rst = '1' THEN
stat <= '0';
cqi <= "0000000000";
wr <= '0';
state <= ST_RST;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
-- 空闲状态
WHEN ST_IDEL =>
stat <= '0';
cqi<= "0000000000";
wr <= '0';
state <= ST_IDEL;
-- 延时等待两个le的周期
WHEN ST_RST =>
IF le= '0' THEN
state <= ST_INIT0;
else
state <= ST_RST;
END IF;
WHEN ST_INIT0 =>
IF le = '1' THEN
state <= ST_INIT1;
else
state <= ST_INIT0;
END IF;
WHEN ST_INIT1=>
IF le = '0' THEN
state <= ST_INIT2;
else
state <= ST_INIT1;
END IF;
WHEN ST_INIT2 =>
IF le = '1' THEN
state <= ST_INIT3;
else
state <= ST_INIT2;
END IF;
WHEN ST_INIT3=>
IF le = '0' THEN
state <= ST_INIT3;
else
state <= ST_LE0;
END IF;
-- 等待le变高好发出wr 信号
WHEN ST_LE0 =>
stat <= '1';
IF le= '0' THEN
state <= ST_LE0;
elsif le = '1' THEN
wr <= '1'; -- 发出写脉冲
state <= ST_WR;
END IF;
WHEN ST_WR =>
-- 发wr信号无效
wr <= '0';
-- addr 增1
cqi <= cqi +1;
IF cqi >= rang then
stat <= '0';
cqi <= "0000000000"; -- 采样个数达到预计值,则进入空闲状态
state <= ST_IDEL;
else
state <= ST_WAIT_LE0; --
end if;
-- 采样个数未达到预计值,等待Le变低
WHEN ST_WAIT_LE0 =>
IF le = '1' THEN
state <= ST_WAIT_LE0;
ELSE
state <= ST_LE0; -- le ='0',进入下一个写入周期
END IF;
WHEN OTHERS =>
stat <= '0';
cqi <= "0000000000";
wr <= '0';
state <= ST_IDEL;
END CASE;
END IF;
END PROCESS;
addr <= cqi;
END a;
大家看看我的程序和仿真的时序,前面的状态机没定义,怎么改? 从CODE看RST＝1之后，状态才有了确定的值。这个不定的值是你的激励造成的（RST信号靠后）。你应从RST＝1之后来分析对否。－－这个现象不是CODE造成的，是激励造成的。
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