我的状态机出现时序滞后，请问高手怎么办
本帖最后由 fpgaw 于 2010-11-19 06:40 编辑程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity pci9054 is
port(lhold: in std_logic;
lholda: out std_logic;
blast: in std_logic;
ads: in std_logic;
lbe: out std_logic_vector(3 downto 0);
ready: out std_logic;
dataout: in std_logic_vector(31 downto 0);
ld: out std_logic_vector(31 downto 0);
lw_r:in std_logic;
bterm:in std_logic;
lreseto:in std_logic;
lclk:in std_logic
);
end pci9054;
architecture behav of pci9054 is
signal shift_val:std_logic;
type state is(s0,s1,s2,s3,s4);
begin
process(blast,lw_r,ads,lclk)
variable p:state;
begin
if (lclk'event and lclk='1')then
case p is
when s0=>if lhold='0' then
p:=s0;
lholda<=lhold;
ready<='0';
elsif lhold='1' then
p:=s1;
lholda<=lhold;
ready<='0';
end if;
when s1=>if ads='1' then
p:=s1;
lholda<=lhold;
ready<='0';
elsif(ads='0' and lw_r='0')then
p:=s3;
ready<='1';
elsif(ads='0' and lw_r='1')then
p:=s2;
ready<='1';
elsif lhold='0'then
p:=s0;
lholda<=lhold;
ready<='0';
end if;
whens2=>if blast='1' then
p:=s2;
ready<='1';
else
p:=s4;
end if;
when s3=>if blast='1' then
p:=s3;
ready<='1';
else
p:=s4;
end if;
when s4=>if( lhold='1' and blast='0') then
p:=s1;
lholda<=lhold;
ready<='0';
elsif( lhold='0' )then
p:=s0;
lholda<=lhold;
ready<='0';
end if;
when others=>null;
end case;
end if;
end process ;
end behav;
我想让lholda跟随lhold变化，但实际上仿真结果是其滞后了三个周期，ready也是如此，请问高手怎么办，并且如果我想让lreseto变高后再进入状态0即初始状态，应该如何更改语句。谢谢！ 3 cycles? you must be kidding
页:
[1]
