求助，不能综合，大家帮忙看一下谢谢1
本帖最后由 fpgaw 于 2010-7-3 05:41 编辑library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
generic(width:integer:=16);
Port (trig: inSTD_LOGIC;
resetn : inSTD_LOGIC;
CS : inSTD_LOGIC;
Slk: inSTD_LOGIC;
Dout : outSTD_LOGIC;
ACK : inoutSTD_LOGIC);
end test;
architecture Behavioral of test is
signal shift_buf: std_logic_vector(width-1 downto 0);
begin
loadshift:process(resetn,trig,count_outQ)
begin
if resetn='0' then
shift_buf<=(others=>'0');
elsif (ACK='1') then
shift_buf<=count_outQ;
end if;
end process loadshift;
shifter:process(Slk)
begin
if (Slk'event and Slk='1') then
elsif CS='1' then
shift_buf<=shl(shift_buf,"1");
shift_buf(0)<='0';
end if;
end process shifter;
Dout<=shift_buf(width-1);
end behavioral;
提示错误：Signal shift_buf<10> cannot be synthesized, bad synchronous description.
大家帮忙看一下谢谢！该程序的简单功能就是计数器的结果并入移位寄存器，然后是移位输出受到外部信号slk和总线使能信号cs的控制输出，
不受其他控制
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