VHDL syntax error at counter10.vhd(32) near
Error (10500): VHDL syntax error at counter10.vhd(32) near text "process";expecting "if"就是说
end process;
这句话有问题
我的源程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter10 is
port (clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(3 downto 0);
dout
ut std_logic_vector(3 downto 0);
c
ut std_logic);
end counter10;
architecture Behavioral of counter10 is
signal count:std_logic_vector(3 downto 0);
begin
dout<=count;
process(clk,reset,din)
begin
if reset='0' then
count<=din;
c<='0';
else if rising_edge(clk) then
if count="1001" then
count<="0000";
c<='1';
else
count<=count+1;
c<='0';
end if;
end if;
end process;
end Behavioral;
请帮忙指点一下怎么改 错误很简单!<br>
但不太容易看!<br>
错误就是 ELSE IF<br>
要么改成IF-ELSIF-END IF组合<br>
要么再加一个END IF; else if 改成 ELSIF 啊~~~~~~~<br>
elsif rising_edge(clk) then<br>
elsif count="1001" then<br>
count<="0000";<br>
c<='1';<br>
else<br>
count<=count+1;<br>
c<='0';<br>
end if; 我在软件上试了一下，这样可以运行，本人也是刚学maxplus2的菜鸟啊～～～～～～<br>
library ieee;<br>
use ieee.std_logic_1164.all;<br>
use ieee.std_logic_arith.all;<br>
use ieee.std_logic_unsigned.all;<br>
entity counter10 is<br>
port (clk:in std_logic;<br>
reset:in std_logic;<br>
din:in std_logic_vector(3 downto 0);<br>
dout
http://bbs.vibesic.com/images/smilies/default/shocked.gif
ut std_logic_vector(3 downto 0);<br>
c
http://bbs.vibesic.com/images/smilies/default/shocked.gif
ut std_logic);<br>
end counter10;<br>
<br>
architecture Behavioral of counter10 is<br>
signal count:std_logic_vector(3 downto 0);<br>
begin<br>
dout<=count;<br>
<br>
process(clk)<br>
begin<br>
if rising_edge(clk) then<br>
if count="1001" then<br>
count<="0000";<br>
c<='1';<br>
else<br>
count<=count+1;<br>
c<='0';<br>
end if;<br>
end if;<br>
end process;<br>
end Behavioral;
页:
[1]
