关于XC3S400控制adc采样问题
编译后报错next_state不能综合，请大家指教。library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test is
port(
clk,busy: in std_logic; -- Clock, nominally 50 MHz
data: in std_logic_Vector(15 downto 0); -- data from adc
convst,rd,cs: out std_logic
);
end test;
architecture Behavioral of test is
type states is ( st0,st1,st2,st3,st4,st5,st6,st7,st8,st9,st10,st11,st12,st13,st14,st15,st16);--定义各状态的子类型
signal current_state, next_state: states :=st16;
signal regl1 :std_logic_vector(15 downto 0);--中间数据寄存信号1
signal regl2 :std_logic_vector(15 downto 0);--中间数据寄存信号2
signal clk_5M: STD_LOGIC:='0';
signal start_adc: STD_LOGIC:='0';
signal con_sample: STD_LOGIC:='0';
signal init_count: STD_LOGIC:='0';
begin
-------------------system use 500 divisior to make 10us to enable adc to convert----------
divisor1: process(clk) --10分频
variable counter : integer range 0 to 5:=0;
begin
if(clk'event and clk = '1') then
current_state <= next_state;
if(counter = 5) then
clk_5M <= not clk_5M;
counter := 0;
else
counter := counter + 1;
end if;
end if;
end process divisor1;
divisor2: process(clk_5M) --50分频与10分频一起使用，用于定时采样，定时时间为10us
variable counter : integer range 0 to 25:=0;
begin
if(clk_5M'event and clk_5M = '1') then
if(counter = 25) then
start_adc <= not start_adc; --Timer 10us enable ADC
counter := 0;
else
counter := counter + 1;
end if;
end if;
end process divisor2;
divisor3: process(clk) --150分频3us时间用于精确的等待ADC转换完成
variable counter : integer range 0 to 150:=0;
begin
if(init_count = '1') then --init_count为定时等待开始标识
if(clk'event and clk = '1') then
if(counter = 150) then
con_sample <= '1'; --con_sample为定时结束，下个状态开始标识
counter := 0;
else
counter := counter +1;
end if;
end if;
else
con_sample <= '0';
end if;
end process divisor3;
-------------------sample state switch---------------------------------------------------
adc_sample: process(current_state,start_adc) --ADC转换(current)
begin
if(start_adc'event and start_adc='1') then
next_state <= st0;
end if;
case current_state is
when st0 => --st0为空闲状态
next_state <= st1;
cs <= '1';
rd <= '1';
convst <= '0';
when st1 => --st1为启动ADC转换状态
next_state <= st2;
cs <= '1';
rd <= '1';
convst <= '1';
when st2 => --st2为等待ADC转换结束状态
if busy = '0' then --如果BUSY没有置高，则继续convst
next_state <= st2;
else
next_state <= st3;
init_count <= '1'; --to start count for 3us wait time
end if;
cs <= '1';
rd <= '1';
convst <= '1';
when st3=> --st3 wait for 3us to complete the convertion
if con_sample = '1' then
init_count <= '0';
next_state <= st4;
else
next_state <= st3;
end if;
cs <= '1';
rd <= '1';
convst <= '1';
when st4 => --read first data ,读取时间为30ns
next_state <= st5;
cs <= '0';
rd <= '1';
convst <= '1';
when st5 => --读取第一个转换值,读取时间为30ns
next_state <= st6;
rd <= '0';
convst <= '1';
cs <= '0';
when st6 => --读取第一个转换值,读取时间为30ns
next_state <= st7;
rd <= '0';
convst <= '1';
cs <= '0';
when st7 => --读取第一个转换值,读取时间为30ns
next_state <= st8;
cs <= '0';
rd <= '0';
convst <= '1';
regl1 <= data;
when st8 => --读取第一个转换值,读取时间为30ns
next_state <= st9;
rd <= '0';
convst <= '1';
cs <= '0';
regl1 <= data;
when st9 => --wait for interval 20ns
next_state <= st10;
cs <= '0';
rd <= '1';
convst <= '1';
when st10 => --wait for interval 20ns
next_state <= st11;
cs <= '0';
rd <= '1';
convst <= '1';
when st11 => --读取第2个转换值,to perform read for 30ns
next_state <= st12;
cs <= '0';
rd <= '0';
convst <= '1';
when st12 => --读取第2个转换值,to perform read for 30ns
next_state <= st13;
cs <= '0';
rd <= '0';
convst <= '1';
when st13 => --读取第2个转换值,读取时间为30ns
next_state <= st14;
cs <= '0';
rd <= '0';
convst <= '1';
regl2 <= data;
when st14 => --读取第2个转换值,读取时间为30ns
next_state <= st15;
cs <= '0';
rd <= '0';
convst <= '1';
regl2 <= data;
when st15 => --to adjust to wait state
next_state <= st16;
cs <= '1';
rd <= '1';
convst <= '1';
when st16 => --to adjust to wait state
cs <= '1';
rd <= '1';
convst <= '0';
when others=>
cs <= '1';
rd <= '1';
convst <= '0';
end case;
end process adc_sample;
-----------------------------------------------------------------------------------------
end Behavioral;
ERROR:Xst:827 - (“路径”) line 98: signal next_state cannot be synthesized, bad synchronous description. 同关注ing 是不是因为给初值了：<br>
signal current_state, next_state: states :=st16; 我的想法和楼上类似 看看了 不错
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