串并转换改错，请大家指出
本帖最后由 fpgaw 于 2010-7-15 13:25 编辑module stop(dataout,clk,datai);
output dataout;
input datain;
input clk;
reg dataout;
reg mem;
reg i,j,k;
initial
begin
i<=0;
j<=0;
end
always @(negedge clk)
begin
if(j==7)
begin
j<=0;
k<=1;
end
else
begin
j<=j+1;
k<=0;
end
end
always @(posedge clk)
begin
mem<=datain;
for(i=0;i>=6;i=i+1)
begin
mem<=mem;
end
end
always @(posedge k)
begin
dataout<=mem;
end
endmodule
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